// CHECK-LABEL: test_vsetq_vgetq_lane_f16 int test_vsetq_vgetq_lane_f16(float16x8_t a) { float16x8_t b; b = vsetq_lane_f16(3.5, a, 5); float16_t c = vgetq_lane_f16(b, 5); return (int)c; // CHECK: movz x{{[0-9]+}}, #3 }
// CHECK: test_vsetq_lane_f16_4 float16x8_t test_vsetq_lane_f16_4(float16x8_t v1, float b, float c) { float16_t a = (float16_t)b + 1.0; return vsetq_lane_f16(a, v1, 7); // CHECK: ins {{v[0-9]+}}.h[7], {{w[0-9]+}} }
// CHECK: test_vsetq_lane_f16_2 float16x8_t test_vsetq_lane_f16_2(float16x8_t v1) { float16_t a = vgetq_lane_f16(v1, 0); return vsetq_lane_f16(a, v1, 7); // CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[0] }
// CHECK: test_vsetq_lane_f16 float16x8_t test_vsetq_lane_f16(float16x8_t v1) { float16_t a; return vsetq_lane_f16(a, v1, 7); // CHECK: fmov {{s[0-9]+}}, wzr // CHECK-NEXT: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[0] }
float16x8_t test_vsetq_lane_f16(float16_t *a1, float16x8_t a2) { // CHECK-LABEL: test_vsetq_lane_f16 return vsetq_lane_f16(*a1, a2, 4); // CHECK insertelement <8 x i16> %a2, i16 %a1, i32 4 }
// CHECK-LABEL: test4_vsetq_lane_f16 float16x8_t test4_vsetq_lane_f16(float16x8_t v1, float b, float c) { float16_t a = (float16_t)b; return vsetq_lane_f16(a, v1, 7); // CHECK: fmov {{w[0-9]+}}, {{s[0-9]+}} // CHECK: ins {{v[0-9]+}}.h[7], {{w[0-9]+}} }
// CHECK-LABEL: test2_vsetq_lane_f16 float16x8_t test2_vsetq_lane_f16(float16x8_t v1) { float16_t a = 1.0; return vsetq_lane_f16(a, v1, 7); // CHECK: movz {{w[0-9]+}}, #15360 // CHECK-NEXT: ins {{v[0-9]+}}.h[7], {{w[0-9]+}} }
// CHECK-LABEL: test_vsetq_lane_f16 float16x8_t test_vsetq_lane_f16(float16x8_t v1) { float16_t a = 0.0; return vsetq_lane_f16(a, v1, 7); // CHECK: ins {{v[0-9]+}}.h[7], wzr }
float16x8_t test_vsetq_lane_f16(float16_t *a, float16x8_t b) { // CHECK-LABEL: test_vsetq_lane_f16: // CHECK-NEXT: ld1.h { v0 }[7], [x0] // CHECK-NEXT: ret return vsetq_lane_f16(*a, b, 7); }
float16x8_t test_vsetq_lane_f16(float16_t *a1, float16x8_t a2) { // CHECK-LABEL: test_vsetq_lane_f16 return vsetq_lane_f16(*a1, a2, 4); // CHECK: [[A1:%[0-9]+]] = load i16, i16* %a1 // CHECK: insertelement <8 x i16> %a2, i16 [[A1]], i32 4 }
// CHECK-LABEL: define <8 x half> @test_vsetq_lane_f16(half* %a, <8 x half> %b) #0 { // CHECK: [[__REINT_248:%.*]] = alloca half, align 2 // CHECK: [[__REINT1_248:%.*]] = alloca <8 x half>, align 16 // CHECK: [[__REINT2_248:%.*]] = alloca <8 x i16>, align 16 // CHECK: [[TMP0:%.*]] = load half, half* %a, align 2 // CHECK: store half [[TMP0]], half* [[__REINT_248]], align 2 // CHECK: store <8 x half> %b, <8 x half>* [[__REINT1_248]], align 16 // CHECK: [[TMP1:%.*]] = bitcast half* [[__REINT_248]] to i16* // CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 2 // CHECK: [[TMP3:%.*]] = bitcast <8 x half>* [[__REINT1_248]] to <8 x i16>* // CHECK: [[TMP4:%.*]] = load <8 x i16>, <8 x i16>* [[TMP3]], align 16 // CHECK: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP4]] to <16 x i8> // CHECK: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x i16> // CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[TMP2]], i32 7 // CHECK: store <8 x i16> [[VSET_LANE]], <8 x i16>* [[__REINT2_248]], align 16 // CHECK: [[TMP7:%.*]] = bitcast <8 x i16>* [[__REINT2_248]] to <8 x half>* // CHECK: [[TMP8:%.*]] = load <8 x half>, <8 x half>* [[TMP7]], align 16 // CHECK: ret <8 x half> [[TMP8]] float16x8_t test_vsetq_lane_f16(float16_t *a, float16x8_t b) { return vsetq_lane_f16(*a, b, 7); }