/// Sink an instruction and its associated debug instructions. static void performSink(MachineInstr &MI, MachineBasicBlock &SuccToSinkTo, MachineBasicBlock::iterator InsertPos) { // Collect matching debug values. SmallVector<MachineInstr *, 2> DbgValuesToSink; collectDebugValues(MI, DbgValuesToSink); // If we cannot find a location to use (merge with), then we erase the debug // location to prevent debug-info driven tools from potentially reporting // wrong location information. if (!SuccToSinkTo.empty() && InsertPos != SuccToSinkTo.end()) MI.setDebugLoc(DILocation::getMergedLocation(MI.getDebugLoc(), InsertPos->getDebugLoc())); else MI.setDebugLoc(DebugLoc()); // Move the instruction. MachineBasicBlock *ParentBlock = MI.getParent(); SuccToSinkTo.splice(InsertPos, ParentBlock, MI, ++MachineBasicBlock::iterator(MI)); // Move previously adjacent debug value instructions to the insert position. for (SmallVectorImpl<MachineInstr *>::iterator DBI = DbgValuesToSink.begin(), DBE = DbgValuesToSink.end(); DBI != DBE; ++DBI) { MachineInstr *DbgMI = *DBI; SuccToSinkTo.splice(InsertPos, ParentBlock, DbgMI, ++MachineBasicBlock::iterator(DbgMI)); } }
// runOnMachineBasicBlock - Fill in delay slots for the given basic block. // There is one or two delay slot per delayed instruction. bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; LastFiller = MBB.instr_end(); for (MachineBasicBlock::instr_iterator I = MBB.instr_begin(); I != MBB.instr_end(); ++I) { if (I->getDesc().hasDelaySlot()) { MachineBasicBlock::instr_iterator InstrWithSlot = I; MachineBasicBlock::instr_iterator J = I; // Treat RET specially as it is only instruction with 2 delay slots // generated while all others generated have 1 delay slot. if (I->getOpcode() == Lanai::RET) { // RET is generated as part of epilogue generation and hence we know // what the two instructions preceding it are and that it is safe to // insert RET above them. MachineBasicBlock::reverse_instr_iterator RI(I); assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() && RI->getOperand(0).getReg() == Lanai::FP && RI->getOperand(1).isReg() && RI->getOperand(1).getReg() == Lanai::FP && RI->getOperand(2).isImm() && RI->getOperand(2).getImm() == -8); ++RI; assert(RI->getOpcode() == Lanai::ADD_I_LO && RI->getOperand(0).isReg() && RI->getOperand(0).getReg() == Lanai::SP && RI->getOperand(1).isReg() && RI->getOperand(1).getReg() == Lanai::FP); ++RI; MachineBasicBlock::instr_iterator FI(RI.base()); MBB.splice(std::next(I), &MBB, FI, I); FilledSlots += 2; } else { if (!NopDelaySlotFiller && findDelayInstr(MBB, I, J)) { MBB.splice(std::next(I), &MBB, J); } else { BuildMI(MBB, std::next(I), DebugLoc(), TII->get(Lanai::NOP)); } ++FilledSlots; } Changed = true; // Record the filler instruction that filled the delay slot. // The instruction after it will be visited in the next iteration. LastFiller = ++I; // Bundle the delay slot filler to InstrWithSlot so that the machine // verifier doesn't expect this instruction to be a terminator. MIBundleBuilder(MBB, InstrWithSlot, std::next(LastFiller)); } } return Changed; }
/// runOnMachineBasicBlock - Fill in delay slots for the given basic block. /// We assume there is only one delay slot per delayed instruction. bool Filler:: runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; LastFiller = MBB.instr_end(); for (InstrIter I = MBB.instr_begin(); I != MBB.instr_end(); ++I) if (I->hasDelaySlot()) { ++FilledSlots; Changed = true; InstrIter D; // Delay slot filling is disabled at -O0. if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None) && findDelayInstr(MBB, I, D)) { MBB.splice(llvm::next(I), &MBB, D); ++UsefulSlots; } else BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP)); // Record the filler instruction that filled the delay slot. // The instruction after it will be visited in the next iteration. LastFiller = ++I; // Set InsideBundle bit so that the machine verifier doesn't expect this // instruction to be a terminator. LastFiller->setIsInsideBundle(); } return Changed; }
/// runOnMachineBasicBlock - Fill in delay slots for the given basic block. /// We assume there is only one delay slot per delayed instruction. bool Filler:: runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; LastFiller = MBB.end(); for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) if (I->hasDelaySlot()) { ++FilledSlots; Changed = true; MachineBasicBlock::iterator D; if (EnableDelaySlotFiller && findDelayInstr(MBB, I, D)) { MBB.splice(llvm::next(I), &MBB, D); ++UsefulSlots; } else BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP)); // Record the filler instruction that filled the delay slot. // The instruction after it will be visited in the next iteration. LastFiller = ++I; } return Changed; }
MachineBasicBlock *Mips16TargetLowering:: emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); // To "insert" a SELECT_CC instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the // destination vreg to set, the condition code register to branch on, the // true/false values to select between, and a branch opcode to use. const BasicBlock *LLVM_BB = BB->getBasicBlock(); MachineFunction::iterator It = BB; ++It; // thisMBB: // ... // TrueVal = ... // setcc r1, r2, r3 // bNE r1, r0, copy1MBB // fallthrough --> copy0MBB MachineBasicBlock *thisMBB = BB; MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); F->insert(It, copy0MBB); F->insert(It, sinkMBB); // Transfer the remainder of BB and its successor edges to sinkMBB. sinkMBB->splice(sinkMBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), BB->end()); sinkMBB->transferSuccessorsAndUpdatePHIs(BB); // Next, add the true and fallthrough blocks as its successors. BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg()) .addMBB(sinkMBB); // copy0MBB: // %FalseValue = ... // # fallthrough to sinkMBB BB = copy0MBB; // Update machine-CFG edges BB->addSuccessor(sinkMBB); // sinkMBB: // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] // ... BB = sinkMBB; BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); MI->eraseFromParent(); // The pseudo instruction is gone now. return BB; }
// Split MBB if it has two direct jumps/branches. void MipsLongBranch::splitMBB(MachineBasicBlock *MBB) { ReverseIter End = MBB->rend(); ReverseIter LastBr = getNonDebugInstr(MBB->rbegin(), End); // Return if MBB has no branch instructions. if ((LastBr == End) || (!LastBr->isConditionalBranch() && !LastBr->isUnconditionalBranch())) return; ReverseIter FirstBr = getNonDebugInstr(std::next(LastBr), End); // MBB has only one branch instruction if FirstBr is not a branch // instruction. if ((FirstBr == End) || (!FirstBr->isConditionalBranch() && !FirstBr->isUnconditionalBranch())) return; assert(!FirstBr->isIndirectBranch() && "Unexpected indirect branch found."); // Create a new MBB. Move instructions in MBB to the newly created MBB. MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB->getBasicBlock()); // Insert NewMBB and fix control flow. MachineBasicBlock *Tgt = getTargetMBB(*FirstBr); NewMBB->transferSuccessors(MBB); NewMBB->removeSuccessor(Tgt, true); MBB->addSuccessor(NewMBB); MBB->addSuccessor(Tgt); MF->insert(std::next(MachineFunction::iterator(MBB)), NewMBB); NewMBB->splice(NewMBB->end(), MBB, (++LastBr).base(), MBB->end()); }
/// runOnMachineBasicBlock - Fill in delay slots for the given basic block. /// We assume there is only one delay slot per delayed instruction. /// bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) if (I->hasDelaySlot()) { MachineBasicBlock::iterator D = MBB.end(); MachineBasicBlock::iterator J = I; if (!DisableDelaySlotFiller) D = findDelayInstr(MBB, I); ++FilledSlots; Changed = true; if (D == MBB.end()) BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(SP::NOP)); else MBB.splice(++J, &MBB, D); unsigned structSize = 0; if (needsUnimp(I, structSize)) { MachineBasicBlock::iterator J = I; ++J; //skip the delay filler. BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(SP::UNIMP)).addImm(structSize); } } return Changed; }
/// runOnMachineBasicBlock - Fill in delay slots for the given basic block. /// We assume there is only one delay slot per delayed instruction. bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; for (Iter I = MBB.begin(); I != MBB.end(); ++I) { if (!I->hasDelaySlot()) continue; ++FilledSlots; Changed = true; Iter D; // Delay slot filling is disabled at -O0. if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None) && findDelayInstr(MBB, I, D)) { MBB.splice(llvm::next(I), &MBB, D); ++UsefulSlots; } else BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP)); // Bundle the delay slot filler to the instruction with the delay slot. MIBundleBuilder(MBB, I, llvm::next(llvm::next(I))); } return Changed; }
/// runOnMachineBasicBlock - Fill in delay slots for the given basic block. /// We assume there is only one delay slot per delayed instruction. /// bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; Subtarget = &MBB.getParent()->getSubtarget<SparcSubtarget>(); const TargetInstrInfo *TII = Subtarget->getInstrInfo(); for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) { MachineBasicBlock::iterator MI = I; ++I; // If MI is restore, try combining it with previous inst. if (!DisableDelaySlotFiller && (MI->getOpcode() == SP::RESTORErr || MI->getOpcode() == SP::RESTOREri)) { Changed |= tryCombineRestoreWithPrevInst(MBB, MI); continue; } // TODO: If we ever want to support v7, this needs to be extended // to cover all floating point operations. if (!Subtarget->isV9() && (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD || MI->getOpcode() == SP::FCMPQ)) { BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); Changed = true; continue; } // If MI has no delay slot, skip. if (!MI->hasDelaySlot()) continue; MachineBasicBlock::iterator D = MBB.end(); if (!DisableDelaySlotFiller) D = findDelayInstr(MBB, MI); ++FilledSlots; Changed = true; if (D == MBB.end()) BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); else MBB.splice(I, &MBB, D); unsigned structSize = 0; if (needsUnimp(MI, structSize)) { MachineBasicBlock::iterator J = MI; ++J; // skip the delay filler. assert (J != MBB.end() && "MI needs a delay instruction."); BuildMI(MBB, ++J, MI->getDebugLoc(), TII->get(SP::UNIMP)).addImm(structSize); // Bundle the delay filler and unimp with the instruction. MIBundleBuilder(MBB, MachineBasicBlock::iterator(MI), J); } else { MIBundleBuilder(MBB, MachineBasicBlock::iterator(MI), I); } } return Changed; }
void EmitALUClause(MachineBasicBlock::iterator InsertPos, ClauseFile &Clause, unsigned &CfCount) { CounterPropagateAddr(Clause.first, CfCount); MachineBasicBlock *BB = Clause.first->getParent(); BuildMI(BB, InsertPos->getDebugLoc(), TII->get(AMDGPU::ALU_CLAUSE)) .addImm(CfCount); for (unsigned i = 0, e = Clause.second.size(); i < e; ++i) { BB->splice(InsertPos, BB, Clause.second[i]); } CfCount += Clause.second.size(); }
/// Split the basic block containing MI into two blocks, which are joined by /// an unconditional branch. Update data structures and renumber blocks to /// account for this change and returns the newly created block. MachineBasicBlock *BranchRelaxation::splitBlockBeforeInstr(MachineInstr &MI, MachineBasicBlock *DestBB) { MachineBasicBlock *OrigBB = MI.getParent(); // Create a new MBB for the code after the OrigBB. MachineBasicBlock *NewBB = MF->CreateMachineBasicBlock(OrigBB->getBasicBlock()); MF->insert(++OrigBB->getIterator(), NewBB); // Splice the instructions starting with MI over to NewBB. NewBB->splice(NewBB->end(), OrigBB, MI.getIterator(), OrigBB->end()); // Add an unconditional branch from OrigBB to NewBB. // Note the new unconditional branch is not being recorded. // There doesn't seem to be meaningful DebugInfo available; this doesn't // correspond to anything in the source. TII->insertUnconditionalBranch(*OrigBB, NewBB, DebugLoc()); // Insert an entry into BlockInfo to align it properly with the block numbers. BlockInfo.insert(BlockInfo.begin() + NewBB->getNumber(), BasicBlockInfo()); NewBB->transferSuccessors(OrigBB); OrigBB->addSuccessor(NewBB); OrigBB->addSuccessor(DestBB); // Cleanup potential unconditional branch to successor block. // Note that updateTerminator may change the size of the blocks. NewBB->updateTerminator(); OrigBB->updateTerminator(); // Figure out how large the OrigBB is. As the first half of the original // block, it cannot contain a tablejump. The size includes // the new jump we added. (It should be possible to do this without // recounting everything, but it's very confusing, and this is rarely // executed.) BlockInfo[OrigBB->getNumber()].Size = computeBlockSize(*OrigBB); // Figure out how large the NewMBB is. As the second half of the original // block, it may contain a tablejump. BlockInfo[NewBB->getNumber()].Size = computeBlockSize(*NewBB); // All BBOffsets following these blocks must be modified. adjustBlockOffsets(*OrigBB); // Need to fix live-in lists if we track liveness. if (TRI->trackLivenessAfterRegAlloc(*MF)) computeLiveIns(LiveRegs, *TRI, *NewBB); ++NumSplit; return NewBB; }
// MI is a load-register-on-condition pseudo instruction that could not be // handled as a single hardware instruction. Replace it by a branch sequence. bool SystemZExpandPseudo::expandLOCRMux(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) { MachineFunction &MF = *MBB.getParent(); const BasicBlock *BB = MBB.getBasicBlock(); MachineInstr &MI = *MBBI; DebugLoc DL = MI.getDebugLoc(); unsigned DestReg = MI.getOperand(0).getReg(); unsigned SrcReg = MI.getOperand(2).getReg(); unsigned CCValid = MI.getOperand(3).getImm(); unsigned CCMask = MI.getOperand(4).getImm(); LivePhysRegs LiveRegs(TII->getRegisterInfo()); LiveRegs.addLiveOuts(MBB); for (auto I = std::prev(MBB.end()); I != MBBI; --I) LiveRegs.stepBackward(*I); // Splice MBB at MI, moving the rest of the block into RestMBB. MachineBasicBlock *RestMBB = MF.CreateMachineBasicBlock(BB); MF.insert(std::next(MachineFunction::iterator(MBB)), RestMBB); RestMBB->splice(RestMBB->begin(), &MBB, MI, MBB.end()); RestMBB->transferSuccessors(&MBB); for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I) RestMBB->addLiveIn(*I); // Create a new block MoveMBB to hold the move instruction. MachineBasicBlock *MoveMBB = MF.CreateMachineBasicBlock(BB); MF.insert(std::next(MachineFunction::iterator(MBB)), MoveMBB); MoveMBB->addLiveIn(SrcReg); for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I) MoveMBB->addLiveIn(*I); // At the end of MBB, create a conditional branch to RestMBB if the // condition is false, otherwise fall through to MoveMBB. BuildMI(&MBB, DL, TII->get(SystemZ::BRC)) .addImm(CCValid).addImm(CCMask ^ CCValid).addMBB(RestMBB); MBB.addSuccessor(RestMBB); MBB.addSuccessor(MoveMBB); // In MoveMBB, emit an instruction to move SrcReg into DestReg, // then fall through to RestMBB. TII->copyPhysReg(*MoveMBB, MoveMBB->end(), DL, DestReg, SrcReg, MI.getOperand(2).isKill()); MoveMBB->addSuccessor(RestMBB); NextMBBI = MBB.end(); MI.eraseFromParent(); return true; }
/// Sink instructions into loops if profitable. This especially tries to prevent /// register spills caused by register pressure if there is little to no /// overhead moving instructions into loops. void MachineLICM::SinkIntoLoop() { MachineBasicBlock *Preheader = getCurPreheader(); if (!Preheader) return; SmallVector<MachineInstr *, 8> Candidates; for (MachineBasicBlock::instr_iterator I = Preheader->instr_begin(); I != Preheader->instr_end(); ++I) { // We need to ensure that we can safely move this instruction into the loop. // As such, it must not have side-effects, e.g. such as a call has. if (IsLoopInvariantInst(*I) && !HasLoopPHIUse(&*I)) Candidates.push_back(&*I); } for (MachineInstr *I : Candidates) { const MachineOperand &MO = I->getOperand(0); if (!MO.isDef() || !MO.isReg() || !MO.getReg()) continue; if (!MRI->hasOneDef(MO.getReg())) continue; bool CanSink = true; MachineBasicBlock *B = nullptr; for (MachineInstr &MI : MRI->use_instructions(MO.getReg())) { // FIXME: Come up with a proper cost model that estimates whether sinking // the instruction (and thus possibly executing it on every loop // iteration) is more expensive than a register. // For now assumes that copies are cheap and thus almost always worth it. if (!MI.isCopy()) { CanSink = false; break; } if (!B) { B = MI.getParent(); continue; } B = DT->findNearestCommonDominator(B, MI.getParent()); if (!B) { CanSink = false; break; } } if (!CanSink || !B || B == Preheader) continue; B->splice(B->getFirstNonPHI(), Preheader, I); } }
bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot) const { if (DisableBackwardSearch) return false; RegDefsUses RegDU(TM); MemDefsUses MemDU(MBB.getParent()->getFrameInfo()); ReverseIter Filler; RegDU.init(*Slot); if (!searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU, Filler)) return false; MBB.splice(std::next(Slot), &MBB, std::next(Filler).base()); MIBundleBuilder(MBB, Slot, std::next(Slot, 2)); ++UsefulSlots; return true; }
/// runOnMachineBasicBlock - Fill in delay slots for the given basic block. /// We assume there is only one delay slot per delayed instruction. /// bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) { MachineBasicBlock::iterator MI = I; ++I; // If MI is restore, try combining it with previous inst. if (!DisableDelaySlotFiller && (MI->getOpcode() == SP::RESTORErr || MI->getOpcode() == SP::RESTOREri)) { Changed |= tryCombineRestoreWithPrevInst(MBB, MI); continue; } // If MI has no delay slot, skip. if (!MI->hasDelaySlot()) continue; MachineBasicBlock::iterator D = MBB.end(); if (!DisableDelaySlotFiller) D = findDelayInstr(MBB, MI); ++FilledSlots; Changed = true; const TargetInstrInfo *TII = TM.getInstrInfo(); if (D == MBB.end()) BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); else MBB.splice(I, &MBB, D); unsigned structSize = 0; if (needsUnimp(MI, structSize)) { MachineBasicBlock::iterator J = MI; ++J; // skip the delay filler. assert (J != MBB.end() && "MI needs a delay instruction."); BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(SP::UNIMP)).addImm(structSize); } } return Changed; }
bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const { // Can handle only calls. if (DisableForwardSearch || !Slot->isCall()) return false; RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo()); NoMemInstr NM; Iter Filler; RegDU.setCallerSaved(*Slot); if (!searchRange(MBB, std::next(Slot), MBB.end(), RegDU, NM, Slot, Filler)) return false; MBB.splice(std::next(Slot), &MBB, Filler); MIBundleBuilder(MBB, Slot, std::next(Slot, 2)); ++UsefulSlots; return true; }
bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const { // Can handle only calls. if (DisableForwardSearch || !Slot->isCall()) return false; RegDefsUses RegDU(TM); NoMemInstr NM; Iter Filler; RegDU.setCallerSaved(*Slot); if (searchRange(MBB, llvm::next(Slot), MBB.end(), RegDU, NM, Filler)) { MBB.splice(llvm::next(Slot), &MBB, Filler); MIBundleBuilder(MBB, Slot, llvm::next(llvm::next(Slot))); ++UsefulSlots; return true; } return false; }
/// When an instruction is found to only use loop invariant operands that is /// safe to hoist, this instruction is called to do the dirty work. void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) { MachineBasicBlock *Preheader = getCurPreheader(); // Now move the instructions to the predecessor, inserting it before any // terminator instructions. DEBUG(dbgs() << "Hoisting to BB#" << Preheader->getNumber() << " from BB#" << MI->getParent()->getNumber() << ": " << *MI); // Splice the instruction to the preheader. MachineBasicBlock *MBB = MI->getParent(); Preheader->splice(Preheader->getFirstTerminator(), MBB, MI); // Add register to livein list to all the BBs in the current loop since a // loop invariant must be kept live throughout the whole loop. This is // important to ensure later passes do not scavenge the def register. AddToLiveIns(Def); ++NumPostRAHoisted; Changed = true; }
/// runOnMachineBasicBlock - Fill in delay slots for the given basic block. /// Currently, we fill delay slots with NOPs. We assume there is only one /// delay slot per delayed instruction. bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) if (I->getDesc().hasDelaySlot()) { MachineBasicBlock::iterator D = MBB.end(); MachineBasicBlock::iterator J = I; if (!DisableDelaySlotFiller) D = findDelayInstr(MBB,I); ++FilledSlots; Changed = true; if (D == MBB.end()) BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(MBlaze::NOP)); else MBB.splice(++J, &MBB, D); } return Changed; }
/// Split the basic block containing MI into two blocks, which are joined by /// an unconditional branch. Update data structures and renumber blocks to /// account for this change and returns the newly created block. /// NOTE: Successor list of the original BB is out of date after this function, /// and must be updated by the caller! Other transforms follow using this /// utility function, so no point updating now rather than waiting. MachineBasicBlock * AArch64BranchRelaxation::splitBlockBeforeInstr(MachineInstr *MI) { MachineBasicBlock *OrigBB = MI->getParent(); // Create a new MBB for the code after the OrigBB. MachineBasicBlock *NewBB = MF->CreateMachineBasicBlock(OrigBB->getBasicBlock()); MachineFunction::iterator MBBI = OrigBB; ++MBBI; MF->insert(MBBI, NewBB); // Splice the instructions starting with MI over to NewBB. NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end()); // Add an unconditional branch from OrigBB to NewBB. // Note the new unconditional branch is not being recorded. // There doesn't seem to be meaningful DebugInfo available; this doesn't // correspond to anything in the source. BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::B)).addMBB(NewBB); // Insert an entry into BlockInfo to align it properly with the block numbers. BlockInfo.insert(BlockInfo.begin() + NewBB->getNumber(), BasicBlockInfo()); // Figure out how large the OrigBB is. As the first half of the original // block, it cannot contain a tablejump. The size includes // the new jump we added. (It should be possible to do this without // recounting everything, but it's very confusing, and this is rarely // executed.) computeBlockSize(*OrigBB); // Figure out how large the NewMBB is. As the second half of the original // block, it may contain a tablejump. computeBlockSize(*NewBB); // All BBOffsets following these blocks must be modified. adjustBlockOffsets(*OrigBB); ++NumSplit; return NewBB; }
void HexagonCopyToCombine::combine(MachineInstr &I1, MachineInstr &I2, MachineBasicBlock::iterator &MI, bool DoInsertAtI1, bool OptForSize) { // We are going to delete I2. If MI points to I2 advance it to the next // instruction. if (MI == I2.getIterator()) ++MI; // Figure out whether I1 or I2 goes into the lowreg part. unsigned I1DestReg = I1.getOperand(0).getReg(); unsigned I2DestReg = I2.getOperand(0).getReg(); bool IsI1Loreg = (I2DestReg - I1DestReg) == 1; unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg; // Get the double word register. unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, Hexagon::subreg_loreg, &Hexagon::DoubleRegsRegClass); assert(DoubleRegDest != 0 && "Expect a valid register"); // Setup source operands. MachineOperand &LoOperand = IsI1Loreg ? I1.getOperand(1) : I2.getOperand(1); MachineOperand &HiOperand = IsI1Loreg ? I2.getOperand(1) : I1.getOperand(1); // Figure out which source is a register and which a constant. bool IsHiReg = HiOperand.isReg(); bool IsLoReg = LoOperand.isReg(); // There is a combine of two constant extended values into CONST64. bool IsC64 = OptForSize && LoOperand.isImm() && HiOperand.isImm() && isGreaterThanNBitTFRI<16>(I1) && isGreaterThanNBitTFRI<16>(I2); MachineBasicBlock::iterator InsertPt(DoInsertAtI1 ? I1 : I2); // Emit combine. if (IsHiReg && IsLoReg) emitCombineRR(InsertPt, DoubleRegDest, HiOperand, LoOperand); else if (IsHiReg) emitCombineRI(InsertPt, DoubleRegDest, HiOperand, LoOperand); else if (IsLoReg) emitCombineIR(InsertPt, DoubleRegDest, HiOperand, LoOperand); else if (IsC64 && !IsConst64Disabled) emitConst64(InsertPt, DoubleRegDest, HiOperand, LoOperand); else emitCombineII(InsertPt, DoubleRegDest, HiOperand, LoOperand); // Move debug instructions along with I1 if it's being // moved towards I2. if (!DoInsertAtI1 && DbgMItoMove.size() != 0) { // Insert debug instructions at the new location before I2. MachineBasicBlock *BB = InsertPt->getParent(); for (auto NewMI : DbgMItoMove) { // If iterator MI is pointing to DEBUG_VAL, make sure // MI now points to next relevant instruction. if (NewMI == (MachineInstr*)MI) ++MI; BB->splice(InsertPt, BB, NewMI); } } I1.eraseFromParent(); I2.eraseFromParent(); }
MachineBasicBlock* MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI, MachineBasicBlock *BB) const { MachineFunction *F = BB->getParent(); MachineRegisterInfo &RI = F->getRegInfo(); DebugLoc dl = MI->getDebugLoc(); const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); unsigned Opc; const TargetRegisterClass * RC; switch (MI->getOpcode()) { default: assert(0 && "Invalid shift opcode!"); case MSP430::Shl8: Opc = MSP430::SHL8r1; RC = MSP430::GR8RegisterClass; break; case MSP430::Shl16: Opc = MSP430::SHL16r1; RC = MSP430::GR16RegisterClass; break; case MSP430::Sra8: Opc = MSP430::SAR8r1; RC = MSP430::GR8RegisterClass; break; case MSP430::Sra16: Opc = MSP430::SAR16r1; RC = MSP430::GR16RegisterClass; break; case MSP430::Srl8: Opc = MSP430::SAR8r1c; RC = MSP430::GR8RegisterClass; break; case MSP430::Srl16: Opc = MSP430::SAR16r1c; RC = MSP430::GR16RegisterClass; break; } const BasicBlock *LLVM_BB = BB->getBasicBlock(); MachineFunction::iterator I = BB; ++I; // Create loop block MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB); F->insert(I, LoopBB); F->insert(I, RemBB); // Update machine-CFG edges by transferring all successors of the current // block to the block containing instructions after shift. RemBB->splice(RemBB->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); RemBB->transferSuccessorsAndUpdatePHIs(BB); // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB BB->addSuccessor(LoopBB); BB->addSuccessor(RemBB); LoopBB->addSuccessor(RemBB); LoopBB->addSuccessor(LoopBB); unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass); unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass); unsigned ShiftReg = RI.createVirtualRegister(RC); unsigned ShiftReg2 = RI.createVirtualRegister(RC); unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg(); unsigned SrcReg = MI->getOperand(1).getReg(); unsigned DstReg = MI->getOperand(0).getReg(); // BB: // cmp 0, N // je RemBB BuildMI(BB, dl, TII.get(MSP430::CMP8ri)) .addReg(ShiftAmtSrcReg).addImm(0); BuildMI(BB, dl, TII.get(MSP430::JCC)) .addMBB(RemBB) .addImm(MSP430CC::COND_E); // LoopBB: // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB] // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB] // ShiftReg2 = shift ShiftReg // ShiftAmt2 = ShiftAmt - 1; BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) .addReg(SrcReg).addMBB(BB) .addReg(ShiftReg2).addMBB(LoopBB); BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg) .addReg(ShiftAmtSrcReg).addMBB(BB) .addReg(ShiftAmtReg2).addMBB(LoopBB); BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2) .addReg(ShiftReg); BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2) .addReg(ShiftAmtReg).addImm(1); BuildMI(LoopBB, dl, TII.get(MSP430::JCC)) .addMBB(LoopBB) .addImm(MSP430CC::COND_NE); // RemBB: // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB] BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg) .addReg(SrcReg).addMBB(BB) .addReg(ShiftReg2).addMBB(LoopBB); MI->eraseFromParent(); // The pseudo instruction is gone now. return RemBB; }
/// TailDuplicate - If it is profitable, duplicate TailBB's contents in each /// of its predecessors. bool TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB, MachineFunction &MF, SmallVector<MachineBasicBlock*, 8> &TDBBs, SmallVector<MachineInstr*, 16> &Copies) { if (!shouldTailDuplicate(MF, *TailBB)) return false; DEBUG(dbgs() << "\n*** Tail-duplicating BB#" << TailBB->getNumber() << '\n'); // Iterate through all the unique predecessors and tail-duplicate this // block into them, if possible. Copying the list ahead of time also // avoids trouble with the predecessor list reallocating. bool Changed = false; SmallSetVector<MachineBasicBlock*, 8> Preds(TailBB->pred_begin(), TailBB->pred_end()); DenseSet<unsigned> UsedByPhi; getRegsUsedByPHIs(*TailBB, &UsedByPhi); for (SmallSetVector<MachineBasicBlock *, 8>::iterator PI = Preds.begin(), PE = Preds.end(); PI != PE; ++PI) { MachineBasicBlock *PredBB = *PI; assert(TailBB != PredBB && "Single-block loop should have been rejected earlier!"); // EH edges are ignored by AnalyzeBranch. if (PredBB->succ_size() > 1) continue; MachineBasicBlock *PredTBB, *PredFBB; SmallVector<MachineOperand, 4> PredCond; if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) continue; if (!PredCond.empty()) continue; // Don't duplicate into a fall-through predecessor (at least for now). if (PredBB->isLayoutSuccessor(TailBB) && PredBB->canFallThrough()) continue; DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB << "From Succ: " << *TailBB); TDBBs.push_back(PredBB); // Remove PredBB's unconditional branch. TII->RemoveBranch(*PredBB); // Clone the contents of TailBB into PredBB. DenseMap<unsigned, unsigned> LocalVRMap; SmallVector<std::pair<unsigned,unsigned>, 4> CopyInfos; MachineBasicBlock::iterator I = TailBB->begin(); while (I != TailBB->end()) { MachineInstr *MI = &*I; ++I; if (MI->isPHI()) { // Replace the uses of the def of the PHI with the register coming // from PredBB. ProcessPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos, UsedByPhi, true); } else { // Replace def of virtual registers with new registers, and update // uses with PHI source register or the new registers. DuplicateInstruction(MI, TailBB, PredBB, MF, LocalVRMap, UsedByPhi); } } MachineBasicBlock::iterator Loc = PredBB->getFirstTerminator(); for (unsigned i = 0, e = CopyInfos.size(); i != e; ++i) { Copies.push_back(BuildMI(*PredBB, Loc, DebugLoc(), TII->get(TargetOpcode::COPY), CopyInfos[i].first).addReg(CopyInfos[i].second)); } // Simplify TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true); NumInstrDups += TailBB->size() - 1; // subtract one for removed branch // Update the CFG. PredBB->removeSuccessor(PredBB->succ_begin()); assert(PredBB->succ_empty() && "TailDuplicate called on block with multiple successors!"); for (MachineBasicBlock::succ_iterator I = TailBB->succ_begin(), E = TailBB->succ_end(); I != E; ++I) PredBB->addSuccessor(*I); Changed = true; ++NumTailDups; } // If TailBB was duplicated into all its predecessors except for the prior // block, which falls through unconditionally, move the contents of this // block into the prior block. MachineBasicBlock *PrevBB = prior(MachineFunction::iterator(TailBB)); MachineBasicBlock *PriorTBB = 0, *PriorFBB = 0; SmallVector<MachineOperand, 4> PriorCond; // This has to check PrevBB->succ_size() because EH edges are ignored by // AnalyzeBranch. if (PrevBB->succ_size() == 1 && !TII->AnalyzeBranch(*PrevBB, PriorTBB, PriorFBB, PriorCond, true) && PriorCond.empty() && !PriorTBB && TailBB->pred_size() == 1 && !TailBB->hasAddressTaken()) { DEBUG(dbgs() << "\nMerging into block: " << *PrevBB << "From MBB: " << *TailBB); if (PreRegAlloc) { DenseMap<unsigned, unsigned> LocalVRMap; SmallVector<std::pair<unsigned,unsigned>, 4> CopyInfos; MachineBasicBlock::iterator I = TailBB->begin(); // Process PHI instructions first. while (I != TailBB->end() && I->isPHI()) { // Replace the uses of the def of the PHI with the register coming // from PredBB. MachineInstr *MI = &*I++; ProcessPHI(MI, TailBB, PrevBB, LocalVRMap, CopyInfos, UsedByPhi, true); if (MI->getParent()) MI->eraseFromParent(); } // Now copy the non-PHI instructions. while (I != TailBB->end()) { // Replace def of virtual registers with new registers, and update // uses with PHI source register or the new registers. MachineInstr *MI = &*I++; DuplicateInstruction(MI, TailBB, PrevBB, MF, LocalVRMap, UsedByPhi); MI->eraseFromParent(); } MachineBasicBlock::iterator Loc = PrevBB->getFirstTerminator(); for (unsigned i = 0, e = CopyInfos.size(); i != e; ++i) { Copies.push_back(BuildMI(*PrevBB, Loc, DebugLoc(), TII->get(TargetOpcode::COPY), CopyInfos[i].first) .addReg(CopyInfos[i].second)); } } else { // No PHIs to worry about, just splice the instructions over. PrevBB->splice(PrevBB->end(), TailBB, TailBB->begin(), TailBB->end()); } PrevBB->removeSuccessor(PrevBB->succ_begin()); assert(PrevBB->succ_empty()); PrevBB->transferSuccessors(TailBB); TDBBs.push_back(PrevBB); Changed = true; } // If this is after register allocation, there are no phis to fix. if (!PreRegAlloc) return Changed; // If we made no changes so far, we are safe. if (!Changed) return Changed; // Handle the nasty case in that we duplicated a block that is part of a loop // into some but not all of its predecessors. For example: // 1 -> 2 <-> 3 | // \ | // \---> rest | // if we duplicate 2 into 1 but not into 3, we end up with // 12 -> 3 <-> 2 -> rest | // \ / | // \----->-----/ | // If there was a "var = phi(1, 3)" in 2, it has to be ultimately replaced // with a phi in 3 (which now dominates 2). // What we do here is introduce a copy in 3 of the register defined by the // phi, just like when we are duplicating 2 into 3, but we don't copy any // real instructions or remove the 3 -> 2 edge from the phi in 2. for (SmallSetVector<MachineBasicBlock *, 8>::iterator PI = Preds.begin(), PE = Preds.end(); PI != PE; ++PI) { MachineBasicBlock *PredBB = *PI; if (std::find(TDBBs.begin(), TDBBs.end(), PredBB) != TDBBs.end()) continue; // EH edges if (PredBB->succ_size() != 1) continue; DenseMap<unsigned, unsigned> LocalVRMap; SmallVector<std::pair<unsigned,unsigned>, 4> CopyInfos; MachineBasicBlock::iterator I = TailBB->begin(); // Process PHI instructions first. while (I != TailBB->end() && I->isPHI()) { // Replace the uses of the def of the PHI with the register coming // from PredBB. MachineInstr *MI = &*I++; ProcessPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos, UsedByPhi, false); } MachineBasicBlock::iterator Loc = PredBB->getFirstTerminator(); for (unsigned i = 0, e = CopyInfos.size(); i != e; ++i) { Copies.push_back(BuildMI(*PredBB, Loc, DebugLoc(), TII->get(TargetOpcode::COPY), CopyInfos[i].first).addReg(CopyInfos[i].second)); } } return Changed; }
bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n" << "********** Function: " << MF.getName() << "\n"); if (skipFunction(*MF.getFunction())) return false; // If we move NewValueJump before register allocation we'll need live variable // analysis here too. QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); QRI = static_cast<const HexagonRegisterInfo *>( MF.getSubtarget().getRegisterInfo()); MBPI = &getAnalysis<MachineBranchProbabilityInfo>(); if (DisableNewValueJumps) { return false; } int nvjCount = DbgNVJCount; int nvjGenerated = 0; // Loop through all the bb's of the function for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end(); MBBb != MBBe; ++MBBb) { MachineBasicBlock *MBB = &*MBBb; DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n"); DEBUG(MBB->dump()); DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n"); bool foundJump = false; bool foundCompare = false; bool invertPredicate = false; unsigned predReg = 0; // predicate reg of the jump. unsigned cmpReg1 = 0; int cmpOp2 = 0; bool MO1IsKill = false; bool MO2IsKill = false; MachineBasicBlock::iterator jmpPos; MachineBasicBlock::iterator cmpPos; MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr; MachineBasicBlock *jmpTarget = nullptr; bool afterRA = false; bool isSecondOpReg = false; bool isSecondOpNewified = false; // Traverse the basic block - bottom up for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin(); MII != E;) { MachineInstr &MI = *--MII; if (MI.isDebugValue()) { continue; } if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated)) break; DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n"); if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt || MI.getOpcode() == Hexagon::J2_jumpf || MI.getOpcode() == Hexagon::J2_jumptnewpt || MI.getOpcode() == Hexagon::J2_jumptnew || MI.getOpcode() == Hexagon::J2_jumpfnewpt || MI.getOpcode() == Hexagon::J2_jumpfnew)) { // This is where you would insert your compare and // instr that feeds compare jmpPos = MII; jmpInstr = &MI; predReg = MI.getOperand(0).getReg(); afterRA = TargetRegisterInfo::isPhysicalRegister(predReg); // If ifconverter had not messed up with the kill flags of the // operands, the following check on the kill flag would suffice. // if(!jmpInstr->getOperand(0).isKill()) break; // This predicate register is live out out of BB // this would only work if we can actually use Live // variable analysis on phy regs - but LLVM does not // provide LV analysis on phys regs. //if(LVs.isLiveOut(predReg, *MBB)) break; // Get all the successors of this block - which will always // be 2. Check if the predicate register is live in in those // successor. If yes, we can not delete the predicate - // I am doing this only because LLVM does not provide LiveOut // at the BB level. bool predLive = false; for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(), SIE = MBB->succ_end(); SI != SIE; ++SI) { MachineBasicBlock* succMBB = *SI; if (succMBB->isLiveIn(predReg)) { predLive = true; } } if (predLive) break; if (!MI.getOperand(1).isMBB()) continue; jmpTarget = MI.getOperand(1).getMBB(); foundJump = true; if (MI.getOpcode() == Hexagon::J2_jumpf || MI.getOpcode() == Hexagon::J2_jumpfnewpt || MI.getOpcode() == Hexagon::J2_jumpfnew) { invertPredicate = true; } continue; } // No new value jump if there is a barrier. A barrier has to be in its // own packet. A barrier has zero operands. We conservatively bail out // here if we see any instruction with zero operands. if (foundJump && MI.getNumOperands() == 0) break; if (foundJump && !foundCompare && MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == predReg) { // Not all compares can be new value compare. Arch Spec: 7.6.1.1 if (isNewValueJumpCandidate(MI)) { assert( (MI.getDesc().isCompare()) && "Only compare instruction can be collapsed into New Value Jump"); isSecondOpReg = MI.getOperand(2).isReg(); if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg, afterRA, jmpPos, MF)) break; cmpInstr = &MI; cmpPos = MII; foundCompare = true; // We need cmpReg1 and cmpOp2(imm or reg) while building // new value jump instruction. cmpReg1 = MI.getOperand(1).getReg(); if (MI.getOperand(1).isKill()) MO1IsKill = true; if (isSecondOpReg) { cmpOp2 = MI.getOperand(2).getReg(); if (MI.getOperand(2).isKill()) MO2IsKill = true; } else cmpOp2 = MI.getOperand(2).getImm(); continue; } } if (foundCompare && foundJump) { // If "common" checks fail, bail out on this BB. if (!commonChecksToProhibitNewValueJump(afterRA, MII)) break; bool foundFeeder = false; MachineBasicBlock::iterator feederPos = MII; if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() && (MI.getOperand(0).getReg() == cmpReg1 || (isSecondOpReg && MI.getOperand(0).getReg() == (unsigned)cmpOp2))) { unsigned feederReg = MI.getOperand(0).getReg(); // First try to see if we can get the feeder from the first operand // of the compare. If we can not, and if secondOpReg is true // (second operand of the compare is also register), try that one. // TODO: Try to come up with some heuristic to figure out which // feeder would benefit. if (feederReg == cmpReg1) { if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) { if (!isSecondOpReg) break; else continue; } else foundFeeder = true; } if (!foundFeeder && isSecondOpReg && feederReg == (unsigned) cmpOp2) if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) break; if (isSecondOpReg) { // In case of CMPLT, or CMPLTU, or EQ with the second register // to newify, swap the operands. if (cmpInstr->getOpcode() == Hexagon::C2_cmpeq && feederReg == (unsigned) cmpOp2) { unsigned tmp = cmpReg1; bool tmpIsKill = MO1IsKill; cmpReg1 = cmpOp2; MO1IsKill = MO2IsKill; cmpOp2 = tmp; MO2IsKill = tmpIsKill; } // Now we have swapped the operands, all we need to check is, // if the second operand (after swap) is the feeder. // And if it is, make a note. if (feederReg == (unsigned)cmpOp2) isSecondOpNewified = true; } // Now that we are moving feeder close the jump, // make sure we are respecting the kill values of // the operands of the feeder. bool updatedIsKill = false; for (unsigned i = 0; i < MI.getNumOperands(); i++) { MachineOperand &MO = MI.getOperand(i); if (MO.isReg() && MO.isUse()) { unsigned feederReg = MO.getReg(); for (MachineBasicBlock::iterator localII = feederPos, end = jmpPos; localII != end; localII++) { MachineInstr &localMI = *localII; for (unsigned j = 0; j < localMI.getNumOperands(); j++) { MachineOperand &localMO = localMI.getOperand(j); if (localMO.isReg() && localMO.isUse() && localMO.isKill() && feederReg == localMO.getReg()) { // We found that there is kill of a use register // Set up a kill flag on the register localMO.setIsKill(false); MO.setIsKill(); updatedIsKill = true; break; } } if (updatedIsKill) break; } } if (updatedIsKill) break; } MBB->splice(jmpPos, MI.getParent(), MI); MBB->splice(jmpPos, MI.getParent(), cmpInstr); DebugLoc dl = MI.getDebugLoc(); MachineInstr *NewMI; assert((isNewValueJumpCandidate(*cmpInstr)) && "This compare is not a New Value Jump candidate."); unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2, isSecondOpNewified, jmpTarget, MBPI); if (invertPredicate) opc = QII->getInvertedPredicatedOpcode(opc); if (isSecondOpReg) NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc)) .addReg(cmpReg1, getKillRegState(MO1IsKill)) .addReg(cmpOp2, getKillRegState(MO2IsKill)) .addMBB(jmpTarget); else if ((cmpInstr->getOpcode() == Hexagon::C2_cmpeqi || cmpInstr->getOpcode() == Hexagon::C2_cmpgti) && cmpOp2 == -1 ) // Corresponding new-value compare jump instructions don't have the // operand for -1 immediate value. NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc)) .addReg(cmpReg1, getKillRegState(MO1IsKill)) .addMBB(jmpTarget); else NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc)) .addReg(cmpReg1, getKillRegState(MO1IsKill)) .addImm(cmpOp2) .addMBB(jmpTarget); assert(NewMI && "New Value Jump Instruction Not created!"); (void)NewMI; if (cmpInstr->getOperand(0).isReg() && cmpInstr->getOperand(0).isKill()) cmpInstr->getOperand(0).setIsKill(false); if (cmpInstr->getOperand(1).isReg() && cmpInstr->getOperand(1).isKill()) cmpInstr->getOperand(1).setIsKill(false); cmpInstr->eraseFromParent(); jmpInstr->eraseFromParent(); ++nvjGenerated; ++NumNVJGenerated; break; } } } } return true; }
/// Splits a MachineBasicBlock to branch before \p SplitBefore. The original /// branch is \p OrigBranch. The target of the new branch can either be the same /// as the target of the original branch or the fallthrough successor of the /// original block as determined by \p BranchToFallThrough. The branch /// conditions will be inverted according to \p InvertNewBranch and /// \p InvertOrigBranch. If an instruction that previously fed the branch is to /// be deleted, it is provided in \p MIToDelete and \p NewCond will be used as /// the branch condition. The branch probabilities will be set if the /// MachineBranchProbabilityInfo isn't null. static bool splitMBB(BlockSplitInfo &BSI) { assert(BSI.allInstrsInSameMBB() && "All instructions must be in the same block."); MachineBasicBlock *ThisMBB = BSI.OrigBranch->getParent(); MachineFunction *MF = ThisMBB->getParent(); MachineRegisterInfo *MRI = &MF->getRegInfo(); assert(MRI->isSSA() && "Can only do this while the function is in SSA form."); if (ThisMBB->succ_size() != 2) { LLVM_DEBUG( dbgs() << "Don't know how to handle blocks that don't have exactly" << " two successors.\n"); return false; } const PPCInstrInfo *TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo(); unsigned OrigBROpcode = BSI.OrigBranch->getOpcode(); unsigned InvertedOpcode = OrigBROpcode == PPC::BC ? PPC::BCn : OrigBROpcode == PPC::BCn ? PPC::BC : OrigBROpcode == PPC::BCLR ? PPC::BCLRn : PPC::BCLR; unsigned NewBROpcode = BSI.InvertNewBranch ? InvertedOpcode : OrigBROpcode; MachineBasicBlock *OrigTarget = BSI.OrigBranch->getOperand(1).getMBB(); MachineBasicBlock *OrigFallThrough = OrigTarget == *ThisMBB->succ_begin() ? *ThisMBB->succ_rbegin() : *ThisMBB->succ_begin(); MachineBasicBlock *NewBRTarget = BSI.BranchToFallThrough ? OrigFallThrough : OrigTarget; BranchProbability ProbToNewTarget = !BSI.MBPI ? BranchProbability::getUnknown() : BSI.MBPI->getEdgeProbability(ThisMBB, NewBRTarget); // Create a new basic block. MachineBasicBlock::iterator InsertPoint = BSI.SplitBefore; const BasicBlock *LLVM_BB = ThisMBB->getBasicBlock(); MachineFunction::iterator It = ThisMBB->getIterator(); MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(LLVM_BB); MF->insert(++It, NewMBB); // Move everything after SplitBefore into the new block. NewMBB->splice(NewMBB->end(), ThisMBB, InsertPoint, ThisMBB->end()); NewMBB->transferSuccessors(ThisMBB); // Add the two successors to ThisMBB. The probabilities come from the // existing blocks if available. ThisMBB->addSuccessor(NewBRTarget, ProbToNewTarget); ThisMBB->addSuccessor(NewMBB, ProbToNewTarget.getCompl()); // Add the branches to ThisMBB. BuildMI(*ThisMBB, ThisMBB->end(), BSI.SplitBefore->getDebugLoc(), TII->get(NewBROpcode)) .addReg(BSI.SplitCond->getOperand(0).getReg()) .addMBB(NewBRTarget); BuildMI(*ThisMBB, ThisMBB->end(), BSI.SplitBefore->getDebugLoc(), TII->get(PPC::B)) .addMBB(NewMBB); if (BSI.MIToDelete) BSI.MIToDelete->eraseFromParent(); // Change the condition on the original branch and invert it if requested. auto FirstTerminator = NewMBB->getFirstTerminator(); if (BSI.NewCond) { assert(FirstTerminator->getOperand(0).isReg() && "Can't update condition of unconditional branch."); FirstTerminator->getOperand(0).setReg(BSI.NewCond->getOperand(0).getReg()); } if (BSI.InvertOrigBranch) FirstTerminator->setDesc(TII->get(InvertedOpcode)); // If any of the PHIs in the successors of NewMBB reference values that // now come from NewMBB, they need to be updated. for (auto *Succ : NewMBB->successors()) { updatePHIs(Succ, ThisMBB, NewMBB, MRI); } addIncomingValuesToPHIs(NewBRTarget, ThisMBB, NewMBB, MRI); LLVM_DEBUG(dbgs() << "After splitting, ThisMBB:\n"; ThisMBB->dump()); LLVM_DEBUG(dbgs() << "NewMBB:\n"; NewMBB->dump()); LLVM_DEBUG(dbgs() << "New branch-to block:\n"; NewBRTarget->dump()); return true; }
MachineBasicBlock * AVM2TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const { const TargetMachine &TM = getTargetMachine(); const TargetInstrInfo &TII = *TM.getInstrInfo(); unsigned BROpcode; DebugLoc dl = MI->getDebugLoc(); bool useIntrin = TM.getSubtarget<AVM2Subtarget>().useIntrinsics(); // Figure out the conditional branch opcode to use for this select_cc. switch (MI->getOpcode()) { default: llvm_unreachable("Unknown SELECT_CC!"); case AVM2::SL: case AVM2::SLF: BROpcode = useIntrin ? AVM2::inCBR : AVM2::asCBR; break; case AVM2::FSL: case AVM2::FSLF: BROpcode = useIntrin ? AVM2::inFCBR : AVM2::asFCBR; break; } // To "insert" a SELECT_CC instruction, we actually have to insert the diamond // control-flow pattern. The incoming instruction knows the destination vreg // to set, the condition code register to branch on, the true/false values to // select between, and a branch opcode to use. const BasicBlock *LLVM_BB = BB->getBasicBlock(); MachineFunction::iterator It = BB; ++It; // thisMBB: // ... // TrueVal = ... // [f]bCC copy1MBB // fallthrough --> copy0MBB MachineBasicBlock *thisMBB = BB; MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); F->insert(It, copy0MBB); F->insert(It, sinkMBB); // Transfer the remainder of BB and its successor edges to sinkMBB. sinkMBB->splice(sinkMBB->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); sinkMBB->transferSuccessorsAndUpdatePHIs(BB); // Add the true and fallthrough blocks as its successors. BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); BuildMI(BB, dl, TII.get(BROpcode)) .addMBB(sinkMBB) .addImm(MI->getOperand(1).getImm()) // CC .addReg(MI->getOperand(2).getReg()) .addReg(MI->getOperand(3).getReg()); // copy0MBB: // %FalseValue = ... // # fallthrough to sinkMBB BB = copy0MBB; // Update machine-CFG edges BB->addSuccessor(sinkMBB); // sinkMBB: // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; BuildMI(*BB, BB->begin(), dl, TII.get(AVM2::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(5).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(4).getReg()).addMBB(thisMBB); MI->eraseFromParent(); // The pseudo instruction is gone now. return BB; }
/// Merge the instructions from SourceRegion.BranchBlock, /// SourceRegion.BranchTargetBlock, and SourceRegion.FallThroughBlock into /// TargetRegion.BranchBlock, TargetRegion.BranchTargetBlock and /// TargetRegion.FallThroughBlock respectively. /// /// The successors for blocks in TargetRegion will be updated to use the /// successors from blocks in SourceRegion. Finally, the blocks in SourceRegion /// will be removed from the function. /// /// A region consists of a BranchBlock, a FallThroughBlock, and a /// BranchTargetBlock. Branch coalesce works on patterns where the /// TargetRegion's BranchTargetBlock must also be the SourceRegions's /// BranchBlock. /// /// Before mergeCandidates: /// /// +---------------------------+ /// | TargetRegion.BranchBlock | /// +---------------------------+ /// / | /// / +--------------------------------+ /// | | TargetRegion.FallThroughBlock | /// \ +--------------------------------+ /// \ | /// +----------------------------------+ /// | TargetRegion.BranchTargetBlock | /// | SourceRegion.BranchBlock | /// +----------------------------------+ /// / | /// / +--------------------------------+ /// | | SourceRegion.FallThroughBlock | /// \ +--------------------------------+ /// \ | /// +----------------------------------+ /// | SourceRegion.BranchTargetBlock | /// +----------------------------------+ /// /// After mergeCandidates: /// /// +-----------------------------+ /// | TargetRegion.BranchBlock | /// | SourceRegion.BranchBlock | /// +-----------------------------+ /// / | /// / +---------------------------------+ /// | | TargetRegion.FallThroughBlock | /// | | SourceRegion.FallThroughBlock | /// \ +---------------------------------+ /// \ | /// +----------------------------------+ /// | SourceRegion.BranchTargetBlock | /// +----------------------------------+ /// /// \param[in] SourceRegion The candidate to move blocks from /// \param[in] TargetRegion The candidate to move blocks to /// bool PPCBranchCoalescing::mergeCandidates(CoalescingCandidateInfo &SourceRegion, CoalescingCandidateInfo &TargetRegion) { if (SourceRegion.MustMoveUp && SourceRegion.MustMoveDown) { llvm_unreachable("Cannot have both MustMoveDown and MustMoveUp set!"); return false; } if (!validateCandidates(SourceRegion, TargetRegion)) return false; // Start the merging process by first handling the BranchBlock. // Move any PHIs in SourceRegion.BranchBlock down to the branch-taken block moveAndUpdatePHIs(SourceRegion.BranchBlock, SourceRegion.BranchTargetBlock); // Move remaining instructions in SourceRegion.BranchBlock into // TargetRegion.BranchBlock MachineBasicBlock::iterator firstInstr = SourceRegion.BranchBlock->getFirstNonPHI(); MachineBasicBlock::iterator lastInstr = SourceRegion.BranchBlock->getFirstTerminator(); MachineBasicBlock *Source = SourceRegion.MustMoveDown ? SourceRegion.BranchTargetBlock : TargetRegion.BranchBlock; MachineBasicBlock::iterator Target = SourceRegion.MustMoveDown ? SourceRegion.BranchTargetBlock->getFirstNonPHI() : TargetRegion.BranchBlock->getFirstTerminator(); Source->splice(Target, SourceRegion.BranchBlock, firstInstr, lastInstr); // Once PHI and instructions have been moved we need to clean up the // control flow. // Remove SourceRegion.FallThroughBlock before transferring successors of // SourceRegion.BranchBlock to TargetRegion.BranchBlock. SourceRegion.BranchBlock->removeSuccessor(SourceRegion.FallThroughBlock); TargetRegion.BranchBlock->transferSuccessorsAndUpdatePHIs( SourceRegion.BranchBlock); // Update branch in TargetRegion.BranchBlock to jump to // SourceRegion.BranchTargetBlock // In this case, TargetRegion.BranchTargetBlock == SourceRegion.BranchBlock. TargetRegion.BranchBlock->ReplaceUsesOfBlockWith( SourceRegion.BranchBlock, SourceRegion.BranchTargetBlock); // Remove the branch statement(s) in SourceRegion.BranchBlock MachineBasicBlock::iterator I = SourceRegion.BranchBlock->terminators().begin(); while (I != SourceRegion.BranchBlock->terminators().end()) { MachineInstr &CurrInst = *I; ++I; if (CurrInst.isBranch()) CurrInst.eraseFromParent(); } // Fall-through block should be empty since this is part of the condition // to coalesce the branches. assert(TargetRegion.FallThroughBlock->empty() && "FallThroughBlocks should be empty!"); // Transfer successor information and move PHIs down to the // branch-taken block. TargetRegion.FallThroughBlock->transferSuccessorsAndUpdatePHIs( SourceRegion.FallThroughBlock); TargetRegion.FallThroughBlock->removeSuccessor(SourceRegion.BranchBlock); // Remove the blocks from the function. assert(SourceRegion.BranchBlock->empty() && "Expecting branch block to be empty!"); SourceRegion.BranchBlock->eraseFromParent(); assert(SourceRegion.FallThroughBlock->empty() && "Expecting fall-through block to be empty!\n"); SourceRegion.FallThroughBlock->eraseFromParent(); NumBlocksCoalesced++; return true; }
//===----------------------------------------------------------------------===// // Lower helper functions //===----------------------------------------------------------------------===// MachineBasicBlock* MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); DebugLoc dl = MI->getDebugLoc(); switch (MI->getOpcode()) { default: assert(false && "Unexpected instr type to insert"); case MBlaze::ShiftRL: case MBlaze::ShiftRA: case MBlaze::ShiftL: { // To "insert" a shift left instruction, we actually have to insert a // simple loop. The incoming instruction knows the destination vreg to // set, the source vreg to operate over and the shift amount. const BasicBlock *LLVM_BB = BB->getBasicBlock(); MachineFunction::iterator It = BB; ++It; // start: // andi samt, samt, 31 // beqid samt, finish // add dst, src, r0 // loop: // addik samt, samt, -1 // sra dst, dst // bneid samt, loop // nop // finish: MachineFunction *F = BB->getParent(); MachineRegisterInfo &R = F->getRegInfo(); MachineBasicBlock *loop = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *finish = F->CreateMachineBasicBlock(LLVM_BB); F->insert(It, loop); F->insert(It, finish); // Update machine-CFG edges by transfering adding all successors and // remaining instructions from the current block to the new block which // will contain the Phi node for the select. finish->splice(finish->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); finish->transferSuccessorsAndUpdatePHIs(BB); // Add the true and fallthrough blocks as its successors. BB->addSuccessor(loop); BB->addSuccessor(finish); // Next, add the finish block as a successor of the loop block loop->addSuccessor(finish); loop->addSuccessor(loop); unsigned IAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass); BuildMI(BB, dl, TII->get(MBlaze::ANDI), IAMT) .addReg(MI->getOperand(2).getReg()) .addImm(31); unsigned IVAL = R.createVirtualRegister(MBlaze::GPRRegisterClass); BuildMI(BB, dl, TII->get(MBlaze::ADDI), IVAL) .addReg(MI->getOperand(1).getReg()) .addImm(0); BuildMI(BB, dl, TII->get(MBlaze::BEQID)) .addReg(IAMT) .addMBB(finish); unsigned DST = R.createVirtualRegister(MBlaze::GPRRegisterClass); unsigned NDST = R.createVirtualRegister(MBlaze::GPRRegisterClass); BuildMI(loop, dl, TII->get(MBlaze::PHI), DST) .addReg(IVAL).addMBB(BB) .addReg(NDST).addMBB(loop); unsigned SAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass); unsigned NAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass); BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT) .addReg(IAMT).addMBB(BB) .addReg(NAMT).addMBB(loop); if (MI->getOpcode() == MBlaze::ShiftL) BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST); else if (MI->getOpcode() == MBlaze::ShiftRA) BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST); else if (MI->getOpcode() == MBlaze::ShiftRL) BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST); else llvm_unreachable("Cannot lower unknown shift instruction"); BuildMI(loop, dl, TII->get(MBlaze::ADDI), NAMT) .addReg(SAMT) .addImm(-1); BuildMI(loop, dl, TII->get(MBlaze::BNEID)) .addReg(NAMT) .addMBB(loop); BuildMI(*finish, finish->begin(), dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg()) .addReg(IVAL).addMBB(BB) .addReg(NDST).addMBB(loop); // The pseudo instruction is no longer needed so remove it MI->eraseFromParent(); return finish; } case MBlaze::Select_FCC: case MBlaze::Select_CC: { // To "insert" a SELECT_CC instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the // destination vreg to set, the condition code register to branch on, the // true/false values to select between, and a branch opcode to use. const BasicBlock *LLVM_BB = BB->getBasicBlock(); MachineFunction::iterator It = BB; ++It; // thisMBB: // ... // TrueVal = ... // setcc r1, r2, r3 // bNE r1, r0, copy1MBB // fallthrough --> copy0MBB MachineFunction *F = BB->getParent(); MachineBasicBlock *flsBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *dneBB = F->CreateMachineBasicBlock(LLVM_BB); unsigned Opc; switch (MI->getOperand(4).getImm()) { default: llvm_unreachable("Unknown branch condition"); case MBlazeCC::EQ: Opc = MBlaze::BEQID; break; case MBlazeCC::NE: Opc = MBlaze::BNEID; break; case MBlazeCC::GT: Opc = MBlaze::BGTID; break; case MBlazeCC::LT: Opc = MBlaze::BLTID; break; case MBlazeCC::GE: Opc = MBlaze::BGEID; break; case MBlazeCC::LE: Opc = MBlaze::BLEID; break; } F->insert(It, flsBB); F->insert(It, dneBB); // Transfer the remainder of BB and its successor edges to dneBB. dneBB->splice(dneBB->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); dneBB->transferSuccessorsAndUpdatePHIs(BB); BB->addSuccessor(flsBB); BB->addSuccessor(dneBB); flsBB->addSuccessor(dneBB); BuildMI(BB, dl, TII->get(Opc)) .addReg(MI->getOperand(3).getReg()) .addMBB(dneBB); // sinkMBB: // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... //BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg()) // .addReg(MI->getOperand(1).getReg()).addMBB(flsBB) // .addReg(MI->getOperand(2).getReg()).addMBB(BB); BuildMI(*dneBB, dneBB->begin(), dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(2).getReg()).addMBB(flsBB) .addReg(MI->getOperand(1).getReg()).addMBB(BB); MI->eraseFromParent(); // The pseudo instruction is gone now. return dneBB; } } }
/// Do expand branches and split the basic blocks if necessary. /// Returns true if made any change. bool MSP430BSel::expandBranches(OffsetVector &BlockOffsets) { // For each conditional branch, if the offset to its destination is larger // than the offset field allows, transform it into a long branch sequence // like this: // short branch: // bCC MBB // long branch: // b!CC $PC+6 // b MBB // bool MadeChange = false; for (auto MBB = MF->begin(), E = MF->end(); MBB != E; ++MBB) { unsigned MBBStartOffset = 0; for (auto MI = MBB->begin(), EE = MBB->end(); MI != EE; ++MI) { MBBStartOffset += TII->getInstSizeInBytes(*MI); // If this instruction is not a short branch then skip it. if (MI->getOpcode() != MSP430::JCC && MI->getOpcode() != MSP430::JMP) { continue; } MachineBasicBlock *DestBB = MI->getOperand(0).getMBB(); // Determine the distance from the current branch to the destination // block. MBBStartOffset already includes the size of the current branch // instruction. int BlockDistance = BlockOffsets[DestBB->getNumber()] - BlockOffsets[MBB->getNumber()]; int BranchDistance = BlockDistance - MBBStartOffset; // If this branch is in range, ignore it. if (isInRage(BranchDistance)) { continue; } DEBUG(dbgs() << " Found a branch that needs expanding, BB#" << DestBB->getNumber() << ", Distance " << BranchDistance << "\n"); // If JCC is not the last instruction we need to split the MBB. if (MI->getOpcode() == MSP430::JCC && std::next(MI) != EE) { DEBUG(dbgs() << " Found a basic block that needs to be split, BB#" << MBB->getNumber() << "\n"); // Create a new basic block. MachineBasicBlock *NewBB = MF->CreateMachineBasicBlock(MBB->getBasicBlock()); MF->insert(std::next(MBB), NewBB); // Splice the instructions following MI over to the NewBB. NewBB->splice(NewBB->end(), &*MBB, std::next(MI), MBB->end()); // Update the successor lists. for (MachineBasicBlock *Succ : MBB->successors()) { if (Succ == DestBB) { continue; } MBB->replaceSuccessor(Succ, NewBB); NewBB->addSuccessor(Succ); } // We introduced a new MBB so all following blocks should be numbered // and measured again. measureFunction(BlockOffsets, &*MBB); ++NumSplit; // It may be not necessary to start all over at this point, but it's // safer do this anyway. return true; } MachineInstr &OldBranch = *MI; DebugLoc dl = OldBranch.getDebugLoc(); int InstrSizeDiff = -TII->getInstSizeInBytes(OldBranch); if (MI->getOpcode() == MSP430::JCC) { MachineBasicBlock *NextMBB = &*std::next(MBB); assert(MBB->isSuccessor(NextMBB) && "This block must have a layout successor!"); // The BCC operands are: // 0. Target MBB // 1. MSP430 branch predicate SmallVector<MachineOperand, 1> Cond; Cond.push_back(MI->getOperand(1)); // Jump over the long branch on the opposite condition TII->reverseBranchCondition(Cond); MI = BuildMI(*MBB, MI, dl, TII->get(MSP430::JCC)) .addMBB(NextMBB) .add(Cond[0]); InstrSizeDiff += TII->getInstSizeInBytes(*MI); ++MI; } // Unconditional branch to the real destination. MI = BuildMI(*MBB, MI, dl, TII->get(MSP430::Bi)).addMBB(DestBB); InstrSizeDiff += TII->getInstSizeInBytes(*MI); // Remove the old branch from the function. OldBranch.eraseFromParent(); // The size of a new instruction is different from the old one, so we need // to correct all block offsets. for (int i = MBB->getNumber() + 1, e = BlockOffsets.size(); i < e; ++i) { BlockOffsets[i] += InstrSizeDiff; } MBBStartOffset += InstrSizeDiff; ++NumExpanded; MadeChange = true; } } return MadeChange; }
/// SinkInstruction - Determine whether it is safe to sink the specified machine /// instruction out of its current block into a successor. bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) { // Don't sink insert_subreg, subreg_to_reg, reg_sequence. These are meant to // be close to the source to make it easier to coalesce. if (AvoidsSinking(MI, MRI)) return false; // Check if it's safe to move the instruction. if (!MI->isSafeToMove(AA, SawStore)) return false; // FIXME: This should include support for sinking instructions within the // block they are currently in to shorten the live ranges. We often get // instructions sunk into the top of a large block, but it would be better to // also sink them down before their first use in the block. This xform has to // be careful not to *increase* register pressure though, e.g. sinking // "x = y + z" down if it kills y and z would increase the live ranges of y // and z and only shrink the live range of x. bool BreakPHIEdge = false; MachineBasicBlock *ParentBlock = MI->getParent(); MachineBasicBlock *SuccToSinkTo = FindSuccToSinkTo(MI, ParentBlock, BreakPHIEdge); // If there are no outputs, it must have side-effects. if (!SuccToSinkTo) return false; // If the instruction to move defines a dead physical register which is live // when leaving the basic block, don't move it because it could turn into a // "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>) for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { const MachineOperand &MO = MI->getOperand(I); if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; if (SuccToSinkTo->isLiveIn(Reg)) return false; } DEBUG(dbgs() << "Sink instr " << *MI << "\tinto block " << *SuccToSinkTo); // If the block has multiple predecessors, this is a critical edge. // Decide if we can sink along it or need to break the edge. if (SuccToSinkTo->pred_size() > 1) { // We cannot sink a load across a critical edge - there may be stores in // other code paths. bool TryBreak = false; bool store = true; if (!MI->isSafeToMove(AA, store)) { DEBUG(dbgs() << " *** NOTE: Won't sink load along critical edge.\n"); TryBreak = true; } // We don't want to sink across a critical edge if we don't dominate the // successor. We could be introducing calculations to new code paths. if (!TryBreak && !DT->dominates(ParentBlock, SuccToSinkTo)) { DEBUG(dbgs() << " *** NOTE: Critical edge found\n"); TryBreak = true; } // Don't sink instructions into a loop. if (!TryBreak && LI->isLoopHeader(SuccToSinkTo)) { DEBUG(dbgs() << " *** NOTE: Loop header found\n"); TryBreak = true; } // Otherwise we are OK with sinking along a critical edge. if (!TryBreak) DEBUG(dbgs() << "Sinking along critical edge.\n"); else { // Mark this edge as to be split. // If the edge can actually be split, the next iteration of the main loop // will sink MI in the newly created block. bool Status = PostponeSplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, BreakPHIEdge); if (!Status) DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to " "break critical edge\n"); // The instruction will not be sunk this time. return false; } } if (BreakPHIEdge) { // BreakPHIEdge is true if all the uses are in the successor MBB being // sunken into and they are all PHI nodes. In this case, machine-sink must // break the critical edge first. bool Status = PostponeSplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, BreakPHIEdge); if (!Status) DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to " "break critical edge\n"); // The instruction will not be sunk this time. return false; } // Determine where to insert into. Skip phi nodes. MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin(); while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI()) ++InsertPos; // collect matching debug values. SmallVector<MachineInstr *, 2> DbgValuesToSink; collectDebugValues(MI, DbgValuesToSink); // Move the instruction. SuccToSinkTo->splice(InsertPos, ParentBlock, MI, ++MachineBasicBlock::iterator(MI)); // Move debug values. for (SmallVectorImpl<MachineInstr *>::iterator DBI = DbgValuesToSink.begin(), DBE = DbgValuesToSink.end(); DBI != DBE; ++DBI) { MachineInstr *DbgMI = *DBI; SuccToSinkTo->splice(InsertPos, ParentBlock, DbgMI, ++MachineBasicBlock::iterator(DbgMI)); } // Conservatively, clear any kill flags, since it's possible that they are no // longer correct. // Note that we have to clear the kill flags for any register this instruction // uses as we may sink over another instruction which currently kills the // used registers. for (MachineOperand &MO : MI->operands()) { if (MO.isReg() && MO.isUse()) RegsToClearKillFlags.set(MO.getReg()); // Remember to clear kill flags. } return true; }