void cgibin_reg_general(WEBBLK *webblk)
{
int i;
REGS *regs;
regs = sysblk.regs[sysblk.pcpu];
if (!regs) regs = &sysblk.dummyregs;
html_header(webblk);
hprintf(webblk->sock, "<H2>General Registers</H2>\n");
hprintf(webblk->sock, "<PRE>\n");
if(regs->arch_mode != ARCH_900)
for (i = 0; i < 16; i++)
hprintf(webblk->sock, "GR%2.2d=%8.8X%s", i, regs->GR_L(i),
((i & 0x03) == 0x03) ? "\n" : "\t");
else
for (i = 0; i < 16; i++)
hprintf(webblk->sock, "GR%1.1X=%16.16" I64_FMT "X%s", i,
(U64)regs->GR_G(i), ((i & 0x03) == 0x03) ? "\n" : " ");
hprintf(webblk->sock, "</PRE>\n");
html_footer(webblk);
}
void cgibin_debug_registers(WEBBLK *webblk)
{
int i, cpu = 0;
int select_gr, select_cr, select_ar;
char *value;
REGS *regs;
if((value = cgi_variable(webblk,"cpu")))
cpu = atoi(value);
if((value = cgi_variable(webblk,"select_gr")) && *value == 'S')
select_gr = 1;
else
select_gr = 0;
if((value = cgi_variable(webblk,"select_cr")) && *value == 'S')
select_cr = 1;
else
select_cr = 0;
if((value = cgi_variable(webblk,"select_ar")) && *value == 'S')
select_ar = 1;
else
select_ar = 0;
/* Validate cpu number */
if (cpu < 0 || cpu >= MAX_CPU || !IS_CPU_ONLINE(cpu))
for (cpu = 0; cpu < MAX_CPU; cpu++)
if(IS_CPU_ONLINE(cpu))
break;
if(cpu < MAX_CPU)
regs = sysblk.regs[cpu];
else
regs = sysblk.regs[sysblk.pcpu];
if (!regs) regs = &sysblk.dummyregs;
if((value = cgi_variable(webblk,"alter_gr")) && *value == 'A')
{
for(i = 0; i < 16; i++)
{
char regname[16];
sprintf(regname,"alter_gr%d",i);
if((value = cgi_variable(webblk,regname)))
{
if(regs->arch_mode != ARCH_900)
sscanf(value,"%"I32_FMT"x",&(regs->GR_L(i)));
else
sscanf(value,"%"I64_FMT"x",&(regs->GR_G(i)));
}
}
}
if((value = cgi_variable(webblk,"alter_cr")) && *value == 'A')
{
for(i = 0; i < 16; i++)
{
char regname[16];
sprintf(regname,"alter_cr%d",i);
if((value = cgi_variable(webblk,regname)))
{
if(regs->arch_mode != ARCH_900)
sscanf(value,"%"I32_FMT"x",&(regs->CR_L(i)));
else
sscanf(value,"%"I64_FMT"x",&(regs->CR_G(i)));
}
}
}
if((value = cgi_variable(webblk,"alter_ar")) && *value == 'A')
{
for(i = 0; i < 16; i++)
{
char regname[16];
sprintf(regname,"alter_ar%d",i);
if((value = cgi_variable(webblk,regname)))
sscanf(value,"%x",&(regs->AR(i)));
}
}
html_header(webblk);
hprintf(webblk->sock,"<form method=post>\n"
"<select type=submit name=cpu>\n");
for(i = 0; i < MAX_CPU; i++)
if(IS_CPU_ONLINE(i))
hprintf(webblk->sock,"<option value=%d%s>CPU%4.4X</option>\n",
i,i==cpu?" selected":"",i);
hprintf(webblk->sock,"</select>\n"
"<input type=submit name=selcpu value=\"Select\">\n"
"<input type=hidden name=cpu value=%d>\n"
"<input type=hidden name=select_gr value=%c>\n"
"<input type=hidden name=select_cr value=%c>\n"
"<input type=hidden name=select_ar value=%c>\n",
cpu, select_gr?'S':'H',select_cr?'S':'H',select_ar?'S':'H');
hprintf(webblk->sock,"Mode: %s\n",get_arch_mode_string(regs));
hprintf(webblk->sock,"</form>\n");
if(!select_gr)
{
hprintf(webblk->sock,"<form method=post>\n"
"<input type=submit name=select_gr "
"value=\"Select General Registers\">\n"
"<input type=hidden name=cpu value=%d>\n"
"<input type=hidden name=select_cr value=%c>\n"
"<input type=hidden name=select_ar value=%c>\n"
"</form>\n",cpu,select_cr?'S':'H',select_ar?'S':'H');
}
else
{
hprintf(webblk->sock,"<form method=post>\n"
"<input type=submit name=select_gr "
"value=\"Hide General Registers\">\n"
"<input type=hidden name=cpu value=%d>\n"
"<input type=hidden name=select_cr value=%c>\n"
"<input type=hidden name=select_ar value=%c>\n"
"</form>\n",cpu,select_cr?'S':'H',select_ar?'S':'H');
hprintf(webblk->sock,"<form method=post>\n"
"<table>\n");
for(i = 0; i < 16; i++)
{
if(regs->arch_mode != ARCH_900)
hprintf(webblk->sock,"%s<td>GR%d</td><td><input type=text name=alter_gr%d size=8 "
"value=%8.8X></td>\n%s",
(i&3)==0?"<tr>\n":"",i,i,regs->GR_L(i),((i&3)==3)?"</tr>\n":"");
else
hprintf(webblk->sock,"%s<td>GR%d</td><td><input type=text name=alter_gr%d size=16 "
"value=%16.16" I64_FMT "X></td>\n%s",
(i&3)==0?"<tr>\n":"",i,i,(U64)regs->GR_G(i),((i&3)==3)?"</tr>\n":"");
}
hprintf(webblk->sock,"</table>\n"
"<input type=submit name=refresh value=\"Refresh\">\n"
"<input type=submit name=alter_gr value=\"Alter\">\n"
"<input type=hidden name=cpu value=%d>\n"
"<input type=hidden name=select_gr value=S>\n"
"<input type=hidden name=select_cr value=%c>\n"
"<input type=hidden name=select_ar value=%c>\n"
"</form>\n",cpu,select_cr?'S':'H',select_ar?'S':'H');
}
if(!select_cr)
{
hprintf(webblk->sock,"<form method=post>\n"
"<input type=submit name=select_cr "
"value=\"Select Control Registers\">\n"
"<input type=hidden name=cpu value=%d>\n"
"<input type=hidden name=select_gr value=%c>\n"
"<input type=hidden name=select_ar value=%c>\n"
"</form>\n",cpu,select_gr?'S':'H',select_ar?'S':'H');
}
else
{
hprintf(webblk->sock,"<form method=post>\n"
"<input type=submit name=select_cr "
"value=\"Hide Control Registers\">\n"
"<input type=hidden name=cpu value=%d>\n"
"<input type=hidden name=select_gr value=%c>\n"
"<input type=hidden name=select_ar value=%c>\n"
"</form>\n",cpu,select_gr?'S':'H',select_ar?'S':'H');
hprintf(webblk->sock,"<form method=post>\n"
"<table>\n");
for(i = 0; i < 16; i++)
{
if(regs->arch_mode != ARCH_900)
hprintf(webblk->sock,"%s<td>CR%d</td><td><input type=text name=alter_cr%d size=8 "
"value=%8.8X></td>\n%s",
(i&3)==0?"<tr>\n":"",i,i,regs->CR_L(i),((i&3)==3)?"</tr>\n":"");
else
hprintf(webblk->sock,"%s<td>CR%d</td><td><input type=text name=alter_cr%d size=16 "
"value=%16.16" I64_FMT "X></td>\n%s",
(i&3)==0?"<tr>\n":"",i,i,(U64)regs->CR_G(i),((i&3)==3)?"</tr>\n":"");
}
hprintf(webblk->sock,"</table>\n"
"<input type=submit name=refresh value=\"Refresh\">\n"
"<input type=submit name=alter_cr value=\"Alter\">\n"
"<input type=hidden name=cpu value=%d>\n"
"<input type=hidden name=select_cr value=S>\n"
"<input type=hidden name=select_gr value=%c>\n"
"<input type=hidden name=select_ar value=%c>\n"
"</form>\n",cpu,select_gr?'S':'H',select_ar?'S':'H');
}
if(regs->arch_mode != ARCH_370)
{
if(!select_ar)
{
hprintf(webblk->sock,"<form method=post>\n"
"<input type=submit name=select_ar "
"value=\"Select Access Registers\">\n"
"<input type=hidden name=cpu value=%d>\n"
"<input type=hidden name=select_gr value=%c>\n"
"<input type=hidden name=select_cr value=%c>\n"
"</form>\n",cpu,select_gr?'S':'H',select_cr?'S':'H');
}
else
{
hprintf(webblk->sock,"<form method=post>\n"
"<input type=submit name=select_ar "
"value=\"Hide Access Registers\">\n"
"<input type=hidden name=cpu value=%d>\n"
"<input type=hidden name=select_gr value=%c>\n"
"<input type=hidden name=select_cr value=%c>\n"
"</form>\n",cpu,select_gr?'S':'H',select_cr?'S':'H');
hprintf(webblk->sock,"<form method=post>\n"
"<table>\n");
for(i = 0; i < 16; i++)
{
hprintf(webblk->sock,"%s<td>AR%d</td><td><input type=text name=alter_ar%d size=8 "
"value=%8.8X></td>\n%s",
(i&3)==0?"<tr>\n":"",i,i,regs->AR(i),((i&3)==3)?"</tr>\n":"");
}
hprintf(webblk->sock,"</table>\n"
"<input type=submit name=refresh value=\"Refresh\">\n"
"<input type=submit name=alter_ar value=\"Alter\">\n"
"<input type=hidden name=cpu value=%d>\n"
"<input type=hidden name=select_gr value=%c>\n"
"<input type=hidden name=select_cr value=%c>\n"
"<input type=hidden name=select_ar value=S>\n"
"</form>\n",cpu,select_gr?'S':'H',select_cr?'S':'H');
}
}
html_footer(webblk);
}
/*-------------------------------------------------------------------*/
int ARCH_DEP(load_ipl) (U16 lcss, U16 devnum, int cpu, int clear)
{
REGS *regs; /* -> Regs */
DEVBLK *dev; /* -> Device control block */
int i; /* Array subscript */
BYTE unitstat; /* IPL device unit status */
BYTE chanstat; /* IPL device channel status */
int rc;
/* Get started */
if ((rc = ARCH_DEP(common_load_begin) (cpu, clear)) )
return rc;
/* Ensure CPU is online */
if (!IS_CPU_ONLINE(cpu))
{
char buf[80];
MSGBUF(buf, "CP%02.2X Offline", devnum);
WRMSG (HHC00810, "E", PTYPSTR(sysblk.pcpu), sysblk.pcpu, buf);
return -1;
}
/* The actual IPL proper starts here... */
regs = sysblk.regs[cpu]; /* Point to IPL CPU's registers */
/* Point to the device block for the IPL device */
dev = find_device_by_devnum (lcss,devnum);
if (dev == NULL)
{
char buf[80];
MSGBUF(buf, "device %4.4X not found", devnum);
WRMSG (HHC00810, "E", PTYPSTR(sysblk.pcpu), sysblk.pcpu, buf);
HDC1(debug_cpu_state, regs);
return -1;
}
if(sysblk.haveiplparm)
{
for(i=0;i<16;i++)
{
regs->GR_L(i)=fetch_fw(&sysblk.iplparmstring[i*4]);
}
sysblk.haveiplparm=0;
}
/* Set Main Storage Reference and Update bits */
STORAGE_KEY(regs->PX, regs) |= (STORKEY_REF | STORKEY_CHANGE);
sysblk.main_clear = sysblk.xpnd_clear = 0;
/* Build the IPL CCW at location 0 */
regs->psa->iplpsw[0] = 0x02; /* CCW command = Read */
regs->psa->iplpsw[1] = 0; /* Data address = zero */
regs->psa->iplpsw[2] = 0;
regs->psa->iplpsw[3] = 0;
regs->psa->iplpsw[4] = CCW_FLAGS_CC | CCW_FLAGS_SLI;
/* CCW flags */
regs->psa->iplpsw[5] = 0; /* Reserved byte */
regs->psa->iplpsw[6] = 0; /* Byte count = 24 */
regs->psa->iplpsw[7] = 24;
/* Enable the subchannel for the IPL device */
dev->pmcw.flag5 |= PMCW5_E;
/* Build the operation request block */ /*@IWZ*/
memset (&dev->orb, 0, sizeof(ORB)); /*@IWZ*/
dev->busy = 1;
RELEASE_INTLOCK(NULL);
/* Execute the IPL channel program */
ARCH_DEP(execute_ccw_chain) (dev);
OBTAIN_INTLOCK(NULL);
/* Clear the interrupt pending and device busy conditions */
obtain_lock (&sysblk.iointqlk);
DEQUEUE_IO_INTERRUPT_QLOCKED(&dev->ioint);
DEQUEUE_IO_INTERRUPT_QLOCKED(&dev->pciioint);
DEQUEUE_IO_INTERRUPT_QLOCKED(&dev->attnioint);
release_lock(&sysblk.iointqlk);
dev->busy = 0;
dev->scsw.flag2 = 0;
dev->scsw.flag3 = 0;
/* Check that load completed normally */
unitstat = dev->scsw.unitstat;
chanstat = dev->scsw.chanstat;
if (unitstat != (CSW_CE | CSW_DE) || chanstat != 0)
{
char buf[80];
char buf2[16];
memset(buf,0,sizeof(buf));
for (i=0; i < (int)dev->numsense; i++)
{
MSGBUF(buf2, "%2.2X", dev->sense[i]);
strlcat(buf, buf2, sizeof(buf) );
if ((i & 3) == 3) strlcat(buf, " ", sizeof(buf));
}
{
char buffer[256];
MSGBUF(buffer, "architecture mode %s, csw status %2.2X%2.2X, sense %s",
get_arch_mode_string((REGS *)0),
unitstat, chanstat, buf);
WRMSG (HHC00828, "E", PTYPSTR(sysblk.pcpu), sysblk.pcpu, buffer);
}
HDC1(debug_cpu_state, regs);
return -1;
}
#ifdef FEATURE_S370_CHANNEL
/* Test the EC mode bit in the IPL PSW */
if (regs->psa->iplpsw[1] & 0x08) {
/* In EC mode, store device address at locations 184-187 */
STORE_FW(regs->psa->ioid, dev->devnum);
} else {
/* In BC mode, store device address at locations 2-3 */
STORE_HW(regs->psa->iplpsw + 2, dev->devnum);
}
#endif /*FEATURE_S370_CHANNEL*/
#ifdef FEATURE_CHANNEL_SUBSYSTEM
/* Set LPUM */
dev->pmcw.lpum = 0x80;
STORE_FW(regs->psa->ioid, (dev->ssid<<16)|dev->subchan);
/* Store zeroes at locations 188-191 */
memset (regs->psa->ioparm, 0, 4);
#endif /*FEATURE_CHANNEL_SUBSYSTEM*/
/* Save IPL device number, cpu number and lcss */
sysblk.ipldev = devnum;
sysblk.iplcpu = regs->cpuad;
sysblk.ipllcss = lcss;
sysblk.ipled = TRUE;
/* Finish up... */
return ARCH_DEP(common_load_finish) (regs);
} /* end function load_ipl */
/*-------------------------------------------------------------------*/
void ARCH_DEP(display_inst) (REGS *iregs, BYTE *inst)
{
QWORD qword; /* Doubleword work area */
BYTE opcode; /* Instruction operation code*/
int ilc; /* Instruction length */
#ifdef DISPLAY_INSTRUCTION_OPERANDS
int b1=-1, b2=-1, x1; /* Register numbers */
VADR addr1 = 0, addr2 = 0; /* Operand addresses */
#endif /*DISPLAY_INSTRUCTION_OPERANDS*/
char buf[256]; /* Message buffer */
int n; /* Number of bytes in buffer */
REGS *regs; /* Copied regs */
if (iregs->ghostregs)
regs = iregs;
else if ((regs = copy_regs(iregs)) == NULL)
return;
#if defined(_FEATURE_SIE)
if(SIE_MODE(regs))
logmsg(_("SIE: "));
#endif /*defined(_FEATURE_SIE)*/
#if 0
#if _GEN_ARCH == 370
logmsg("S/370 ");
#elif _GEN_ARCH == 390
logmsg("ESA/390 ");
#else
logmsg("Z/Arch ");
#endif
#endif
/* Display the PSW */
memset (qword, 0x00, sizeof(qword));
copy_psw (regs, qword);
if(sysblk.cpus>1)
{
n=sprintf(buf,"CPU%4.4X: ",regs->cpuad);
}
else
{
n=0;
}
n += sprintf (buf+n,
"PSW=%2.2X%2.2X%2.2X%2.2X %2.2X%2.2X%2.2X%2.2X ",
qword[0], qword[1], qword[2], qword[3],
qword[4], qword[5], qword[6], qword[7]);
#if defined(FEATURE_ESAME)
n += sprintf (buf + n,
"%2.2X%2.2X%2.2X%2.2X%2.2X%2.2X%2.2X%2.2X ",
qword[8], qword[9], qword[10], qword[11],
qword[12], qword[13], qword[14], qword[15]);
#endif /*defined(FEATURE_ESAME)*/
/* Exit if instruction is not valid */
if (inst == NULL)
{
logmsg (_("%sInstruction fetch error\n"), buf);
display_regs (regs);
if (!iregs->ghostregs) free(regs);
return;
}
/* Extract the opcode and determine the instruction length */
opcode = inst[0];
ilc = ILC(opcode);
/* Show registers associated with the instruction */
if (sysblk.showregsfirst)
display_inst_regs (regs, inst, opcode);
/* Display the instruction */
n += sprintf (buf+n, "INST=%2.2X%2.2X", inst[0], inst[1]);
if (ilc > 2) n += sprintf (buf+n, "%2.2X%2.2X", inst[2], inst[3]);
if (ilc > 4) n += sprintf (buf+n, "%2.2X%2.2X", inst[4], inst[5]);
logmsg ("%s %s", buf,(ilc<4) ? " " : (ilc<6) ? " " : "");
DISASM_INSTRUCTION(inst, buf);
logmsg("%s\n", buf);
#ifdef DISPLAY_INSTRUCTION_OPERANDS
/* Process the first storage operand */
if (ilc > 2
&& opcode != 0x84 && opcode != 0x85
&& opcode != 0xA5 && opcode != 0xA7
&& opcode != 0xB3
&& opcode != 0xC0 && opcode != 0xC4 && opcode != 0xC6
&& opcode != 0xEC)
{
/* Calculate the effective address of the first operand */
b1 = inst[2] >> 4;
addr1 = ((inst[2] & 0x0F) << 8) | inst[3];
if (b1 != 0)
{
addr1 += regs->GR(b1);
addr1 &= ADDRESS_MAXWRAP(regs);
}
/* Apply indexing for RX/RXE/RXF instructions */
if ((opcode >= 0x40 && opcode <= 0x7F) || opcode == 0xB1
|| opcode == 0xE3 || opcode == 0xED)
{
x1 = inst[1] & 0x0F;
if (x1 != 0)
{
addr1 += regs->GR(x1);
addr1 &= ADDRESS_MAXWRAP(regs);
}
}
}
int suspend_cmd(int argc, char *argv[],char *cmdline)
{
char *fn = SR_DEFAULT_FILENAME;
SR_FILE *file;
CPU_BITMAP started_mask;
struct timeval tv;
time_t tt;
int i, j, rc;
REGS *regs;
DEVBLK *dev;
IOINT *ioq;
BYTE psw[16];
UNREFERENCED(cmdline);
if (argc > 2)
{
// "SR: too many arguments"
WRMSG(HHC02000, "E");
return -1;
}
if (argc == 2)
fn = argv[1];
file = SR_OPEN (fn, "wb");
if (file == NULL)
{
// "SR: error in function '%s': '%s'"
WRMSG(HHC02001, "E","open()",strerror(errno));
return -1;
}
TRACE("SR: Begin Suspend Processing...\n");
/* Save CPU state and stop all CPU's */
TRACE("SR: Stopping All CPUs...\n");
OBTAIN_INTLOCK(NULL);
started_mask = sysblk.started_mask;
while (sysblk.started_mask)
{
for (i = 0; i < sysblk.maxcpu; i++)
{
if (IS_CPU_ONLINE(i))
{
sysblk.regs[i]->cpustate = CPUSTATE_STOPPING;
ON_IC_INTERRUPT(sysblk.regs[i]);
signal_condition(&sysblk.regs[i]->intcond);
}
}
RELEASE_INTLOCK(NULL);
usleep (1000);
OBTAIN_INTLOCK(NULL);
}
RELEASE_INTLOCK(NULL);
/* Wait for I/O queue to clear out */
TRACE("SR: Waiting for I/O Queue to clear...\n");
#ifdef OPTION_FISHIO
SLEEP (2);
#else
obtain_lock (&sysblk.ioqlock);
while (sysblk.ioq)
{
release_lock (&sysblk.ioqlock);
usleep (1000);
obtain_lock (&sysblk.ioqlock);
}
release_lock (&sysblk.ioqlock);
#endif
/* Wait for active I/Os to complete */
TRACE("SR: Waiting for Active I/Os to Complete...\n");
for (i = 1; i < 5000; i++)
{
dev = sr_active_devices();
if (dev == NULL) break;
if (i % 500 == 0)
{
// "SR: waiting for device %04X"
WRMSG(HHC02002, "W", dev->devnum);
}
usleep (10000);
}
if (dev != NULL)
{
// "SR: device %04X still busy, proceeding anyway"
WRMSG(HHC02003, "W",dev->devnum);
}
/* Write header */
TRACE("SR: Writing File Header...\n");
SR_WRITE_STRING(file, SR_HDR_ID, SR_ID);
SR_WRITE_STRING(file, SR_HDR_VERSION, VERSION);
gettimeofday(&tv, NULL); tt = tv.tv_sec;
SR_WRITE_STRING(file, SR_HDR_DATE, ctime(&tt));
/* Write system data */
TRACE("SR: Saving System Data...\n");
SR_WRITE_STRING(file,SR_SYS_ARCH_NAME,arch_name[sysblk.arch_mode]);
SR_WRITE_VALUE (file,SR_SYS_STARTED_MASK,started_mask,sizeof(started_mask));
SR_WRITE_VALUE (file,SR_SYS_MAINSIZE,sysblk.mainsize,sizeof(sysblk.mainsize));
TRACE("SR: Saving MAINSTOR...\n");
SR_WRITE_BUF (file,SR_SYS_MAINSTOR,sysblk.mainstor,sysblk.mainsize);
SR_WRITE_VALUE (file,SR_SYS_SKEYSIZE,(sysblk.mainsize/STORAGE_KEY_UNITSIZE),sizeof(U32));
TRACE("SR: Saving Storage Keys...\n");
SR_WRITE_BUF (file,SR_SYS_STORKEYS,sysblk.storkeys,sysblk.mainsize/STORAGE_KEY_UNITSIZE);
SR_WRITE_VALUE (file,SR_SYS_XPNDSIZE,sysblk.xpndsize,sizeof(sysblk.xpndsize));
TRACE("SR: Saving Expanded Storage...\n");
SR_WRITE_BUF (file,SR_SYS_XPNDSTOR,sysblk.xpndstor,4096*sysblk.xpndsize);
SR_WRITE_VALUE (file,SR_SYS_CPUID,sysblk.cpuid,sizeof(sysblk.cpuid));
SR_WRITE_VALUE (file,SR_SYS_IPLDEV,sysblk.ipldev,sizeof(sysblk.ipldev));
SR_WRITE_VALUE (file,SR_SYS_IPLCPU,sysblk.iplcpu,sizeof(sysblk.iplcpu));
SR_WRITE_VALUE (file,SR_SYS_MBO,sysblk.mbo,sizeof(sysblk.mbo));
SR_WRITE_VALUE (file,SR_SYS_MBK,sysblk.mbk,sizeof(sysblk.mbk));
SR_WRITE_VALUE (file,SR_SYS_MBM,sysblk.mbm,sizeof(sysblk.mbm));
SR_WRITE_VALUE (file,SR_SYS_MBD,sysblk.mbd,sizeof(sysblk.mbd));
for (ioq = sysblk.iointq; ioq; ioq = ioq->next)
if (ioq->pcipending)
{
SR_WRITE_VALUE(file,SR_SYS_PCIPENDING_LCSS, SSID_TO_LCSS(ioq->dev->ssid),sizeof(U16));
SR_WRITE_VALUE(file,SR_SYS_PCIPENDING, ioq->dev->devnum,sizeof(ioq->dev->devnum));
}
else if (ioq->attnpending)
{
SR_WRITE_VALUE(file,SR_SYS_ATTNPENDING_LCSS, SSID_TO_LCSS(ioq->dev->ssid),sizeof(U16));
SR_WRITE_VALUE(file,SR_SYS_ATTNPENDING, ioq->dev->devnum,sizeof(ioq->dev->devnum));
}
else
{
SR_WRITE_VALUE(file,SR_SYS_IOPENDING_LCSS, SSID_TO_LCSS(ioq->dev->ssid),sizeof(U16));
SR_WRITE_VALUE(file,SR_SYS_IOPENDING, ioq->dev->devnum,sizeof(ioq->dev->devnum));
}
for (i = 0; i < 8; i++)
SR_WRITE_VALUE(file,SR_SYS_CHP_RESET+i,sysblk.chp_reset[i],sizeof(sysblk.chp_reset[0]));
SR_WRITE_VALUE (file,SR_SYS_SERVPARM,sysblk.servparm,sizeof(sysblk.servparm));
SR_WRITE_VALUE (file,SR_SYS_SIGINTREQ,sysblk.sigintreq,1);
SR_WRITE_STRING(file,SR_SYS_LOADPARM,str_loadparm());
SR_WRITE_VALUE (file,SR_SYS_INTS_STATE,sysblk.ints_state,sizeof(sysblk.ints_state));
SR_WRITE_HDR(file, SR_DELIMITER, 0);
/* Save service console state */
TRACE("SR: Saving Service Console State...\n");
SR_WRITE_HDR(file, SR_SYS_SERVC, 0);
servc_hsuspend(file);
SR_WRITE_HDR(file, SR_DELIMITER, 0);
/* Save clock state */
TRACE("SR: Saving Clock State...\n");
SR_WRITE_HDR(file, SR_SYS_CLOCK, 0);
clock_hsuspend(file);
SR_WRITE_HDR(file, SR_DELIMITER, 0);
/* Write CPU data */
for (i = 0; i < sysblk.maxcpu; i++)
{
if (!IS_CPU_ONLINE(i)) continue;
TRACE("SR: Saving CPU %d Data...\n", i);
regs = sysblk.regs[i];
SR_WRITE_VALUE(file, SR_CPU, i, sizeof(i));
SR_WRITE_VALUE(file, SR_CPU_ARCHMODE, regs->arch_mode,sizeof(regs->arch_mode));
SR_WRITE_VALUE(file, SR_CPU_PX, regs->PX_G,sizeof(regs->PX_G));
copy_psw (regs, psw);
SR_WRITE_BUF(file, SR_CPU_PSW, psw, 16);
for (j = 0; j < 16; j++)
SR_WRITE_VALUE(file, SR_CPU_GR+j, regs->GR_G(j),sizeof(regs->GR_G(0)));
for (j = 0; j < 16; j++)
SR_WRITE_VALUE(file, SR_CPU_CR+j, regs->CR_G(j),sizeof(regs->CR_G(0)));
for (j = 0; j < 16; j++)
SR_WRITE_VALUE(file, SR_CPU_AR+j, regs->ar[j],sizeof(regs->ar[0]));
for (j = 0; j < 32; j++)
SR_WRITE_VALUE(file, SR_CPU_FPR+j, regs->fpr[j],sizeof(regs->fpr[0]));
SR_WRITE_VALUE(file, SR_CPU_FPC, regs->fpc, sizeof(regs->fpc));
SR_WRITE_VALUE(file, SR_CPU_DXC, regs->dxc, sizeof(regs->dxc));
SR_WRITE_VALUE(file, SR_CPU_MC, regs->MC_G, sizeof(regs->MC_G));
SR_WRITE_VALUE(file, SR_CPU_EA, regs->EA_G, sizeof(regs->EA_G));
SR_WRITE_VALUE(file, SR_CPU_PTIMER, cpu_timer(regs), sizeof(S64));
SR_WRITE_VALUE(file, SR_CPU_CLKC, regs->clkc, sizeof(regs->clkc));
SR_WRITE_VALUE(file, SR_CPU_CHANSET, regs->chanset, sizeof(regs->chanset));
SR_WRITE_VALUE(file, SR_CPU_TODPR, regs->todpr, sizeof(regs->todpr));
SR_WRITE_VALUE(file, SR_CPU_MONCLASS, regs->monclass, sizeof(regs->monclass));
SR_WRITE_VALUE(file, SR_CPU_EXCARID, regs->excarid, sizeof(regs->excarid));
SR_WRITE_VALUE(file, SR_CPU_BEAR, regs->bear, sizeof(regs->bear));
SR_WRITE_VALUE(file, SR_CPU_OPNDRID, regs->opndrid, sizeof(regs->opndrid));
SR_WRITE_VALUE(file, SR_CPU_CHECKSTOP, regs->checkstop, 1);
SR_WRITE_VALUE(file, SR_CPU_HOSTINT, regs->hostint, 1);
SR_WRITE_VALUE(file, SR_CPU_EXECFLAG, regs->execflag, 1);
// SR_WRITE_VALUE(file, SR_CPU_INSTVALID, regs->instvalid, 1);
SR_WRITE_VALUE(file, SR_CPU_PERMODE, regs->permode, 1);
SR_WRITE_VALUE(file, SR_CPU_LOADSTATE, regs->loadstate, 1);
SR_WRITE_VALUE(file, SR_CPU_INVALIDATE, regs->invalidate, 1);
SR_WRITE_VALUE(file, SR_CPU_SIGPRESET, regs->sigpreset, 1);
SR_WRITE_VALUE(file, SR_CPU_SIGPIRESET, regs->sigpireset, 1);
SR_WRITE_VALUE(file, SR_CPU_INTS_STATE, regs->ints_state, sizeof(regs->ints_state));
SR_WRITE_VALUE(file, SR_CPU_INTS_MASK, regs->ints_mask, sizeof(regs->ints_mask));
for (j = 0; j < sysblk.maxcpu; j++)
SR_WRITE_VALUE(file, SR_CPU_MALFCPU+j, regs->malfcpu[j], sizeof(regs->malfcpu[0]));
for (j = 0; j < sysblk.maxcpu; j++)
SR_WRITE_VALUE(file, SR_CPU_EMERCPU+j, regs->emercpu[j], sizeof(regs->emercpu[0]));
SR_WRITE_VALUE(file, SR_CPU_EXTCCPU, regs->extccpu, sizeof(regs->extccpu));
SR_WRITE_HDR(file, SR_DELIMITER, 0);
}
/* Write Device data */
for (dev = sysblk.firstdev; dev; dev = dev->nextdev)
{
if (!(dev->pmcw.flag5 & PMCW5_V)) continue;
TRACE("SR: Saving Device %4.4X...\n", dev->devnum);
/* These fields must come first so the device could be attached */
SR_WRITE_VALUE(file, SR_DEV, dev->devnum, sizeof(dev->devnum));
SR_WRITE_VALUE(file, SR_DEV_LCSS, SSID_TO_LCSS(dev->ssid), sizeof(U16));
SR_WRITE_VALUE(file, SR_DEV_ARGC, dev->argc, sizeof(dev->argc));
for (i = 0; i < dev->argc; i++)
if (dev->argv[i])
{
SR_WRITE_STRING(file, SR_DEV_ARGV, dev->argv[i]);
}
else
{
SR_WRITE_STRING(file, SR_DEV_ARGV, "");
}
SR_WRITE_STRING(file, SR_DEV_TYPNAME, dev->typname);
/* Common device fields */
SR_WRITE_BUF (file, SR_DEV_ORB, &dev->orb, sizeof(ORB));
SR_WRITE_BUF (file, SR_DEV_PMCW, &dev->pmcw, sizeof(PMCW));
SR_WRITE_BUF (file, SR_DEV_SCSW, &dev->scsw, sizeof(SCSW));
SR_WRITE_BUF (file, SR_DEV_PCISCSW, &dev->pciscsw, sizeof(SCSW));
SR_WRITE_BUF (file, SR_DEV_ATTNSCSW, &dev->attnscsw, sizeof(SCSW));
SR_WRITE_BUF (file, SR_DEV_CSW, dev->csw, 8);
SR_WRITE_BUF (file, SR_DEV_PCICSW, dev->pcicsw, 8);
SR_WRITE_BUF (file, SR_DEV_ATTNCSW, dev->attncsw, 8);
SR_WRITE_BUF (file, SR_DEV_ESW, &dev->esw, sizeof(ESW));
SR_WRITE_BUF (file, SR_DEV_ECW, dev->ecw, 32);
SR_WRITE_BUF (file, SR_DEV_SENSE, dev->sense, 32);
SR_WRITE_VALUE(file, SR_DEV_PGSTAT, dev->pgstat, sizeof(dev->pgstat));
SR_WRITE_BUF (file, SR_DEV_PGID, dev->pgid, 11);
/* By Adrian - SR_DEV_DRVPWD */
SR_WRITE_BUF (file, SR_DEV_DRVPWD, dev->drvpwd, 11);
SR_WRITE_VALUE(file, SR_DEV_BUSY, dev->busy, 1);
SR_WRITE_VALUE(file, SR_DEV_RESERVED, dev->reserved, 1);
SR_WRITE_VALUE(file, SR_DEV_SUSPENDED, dev->suspended, 1);
SR_WRITE_VALUE(file, SR_DEV_PCIPENDING, dev->pcipending, 1);
SR_WRITE_VALUE(file, SR_DEV_ATTNPENDING, dev->attnpending, 1);
SR_WRITE_VALUE(file, SR_DEV_PENDING, dev->pending, 1);
SR_WRITE_VALUE(file, SR_DEV_STARTPENDING, dev->startpending, 1);
SR_WRITE_VALUE(file, SR_DEV_CRWPENDING, dev->crwpending, 1);
SR_WRITE_VALUE(file, SR_DEV_CCWADDR, dev->ccwaddr, sizeof(dev->ccwaddr));
SR_WRITE_VALUE(file, SR_DEV_IDAPMASK, dev->idapmask, sizeof(dev->idapmask));
SR_WRITE_VALUE(file, SR_DEV_IDAWFMT, dev->idawfmt, sizeof(dev->idawfmt));
SR_WRITE_VALUE(file, SR_DEV_CCWFMT, dev->ccwfmt, sizeof(dev->ccwfmt));
SR_WRITE_VALUE(file, SR_DEV_CCWKEY, dev->ccwkey, sizeof(dev->ccwkey));
/* Device type specific data */
SR_WRITE_VALUE(file, SR_DEV_DEVTYPE, dev->devtype, sizeof(dev->devtype));
if (dev->hnd->hsuspend)
{
rc = (dev->hnd->hsuspend) (dev, file);
if (rc < 0) goto sr_error_exit;
}
SR_WRITE_HDR(file, SR_DELIMITER, 0);
}
TRACE("SR: Writing EOF\n");
SR_WRITE_HDR(file, SR_EOF, 0);
SR_CLOSE (file);
TRACE("SR: Suspend Complete; shutting down...\n");
/* Shutdown */
do_shutdown();
return 0;
sr_error_exit:
// "SR: error processing file '%s'"
WRMSG(HHC02004, "E", fn);
SR_CLOSE (file);
return -1;
}
int resume_cmd(int argc, char *argv[],char *cmdline)
{
char *fn = SR_DEFAULT_FILENAME;
SR_FILE *file;
U32 key = 0, len = 0;
U64 mainsize = 0;
U64 xpndsize = 0;
CPU_BITMAP started_mask = 0;
int i, rc = -1;
REGS *regs = NULL;
U16 devnum=0;
U16 lcss=0;
U16 hw;
int devargc=0;
char *devargv[16];
int devargx=0;
DEVBLK *dev = NULL;
IOINT *ioq = NULL;
char buf[SR_MAX_STRING_LENGTH+1];
char zeros[16];
S64 dreg;
UNREFERENCED(cmdline);
if (argc > 2)
{
// "SR: too many arguments"
WRMSG(HHC02000, "E");
return -1;
}
if (argc == 2)
fn = argv[1];
memset (zeros, 0, sizeof(zeros));
TRACE("SR: Begin Resume Processing...\n");
/* Make sure all CPUs are deconfigured or stopped */
TRACE("SR: Waiting for CPUs to stop...\n");
OBTAIN_INTLOCK(NULL);
for (i = 0; i < sysblk.maxcpu; i++)
if (IS_CPU_ONLINE(i)
&& CPUSTATE_STOPPED != sysblk.regs[i]->cpustate)
{
RELEASE_INTLOCK(NULL);
// "SR: all processors must be stopped to resume"
WRMSG(HHC02005, "E");
return -1;
}
RELEASE_INTLOCK(NULL);
file = SR_OPEN (fn, "rb");
if (file == NULL)
{
// "SR: error in function '%s': '%s'"
WRMSG(HHC02001, "E", "open()",strerror(errno));
return -1;
}
/* First key must be SR_HDR_ID and string must match SR_ID */
TRACE("SR: Reading File Header...\n");
SR_READ_HDR(file, key, len);
if (key == SR_HDR_ID) SR_READ_STRING(file, buf, len);
if (key != SR_HDR_ID || strcmp(buf, SR_ID))
{
// "SR: file identifier error"
WRMSG(HHC02006, "E");
goto sr_error_exit;
}
/* Deconfigure all CPUs */
TRACE("SR: Deconfiguring all CPUs...\n");
OBTAIN_INTLOCK(NULL);
for (i = 0; i < sysblk.maxcpu; i++)
if (IS_CPU_ONLINE(i))
deconfigure_cpu(i);
RELEASE_INTLOCK(NULL);
TRACE("SR: Processing Resume File...\n");
while (key != SR_EOF)
{
SR_READ_HDR(file, key, len);
switch (key) {
case SR_HDR_DATE:
SR_READ_STRING(file, buf, len);
if (len >= 2)
{
len -= 2;
while (len > 0 && isspace(buf[len]))
--len;
buf[len+1]=0;
}
// "SR: resuming suspended file created on '%s'"
WRMSG(HHC02007, "I", buf);
break;
case SR_SYS_STARTED_MASK:
SR_READ_VALUE(file, len, &started_mask, sizeof(started_mask));
break;
case SR_SYS_ARCH_NAME:
SR_READ_STRING(file, buf, len);
i = -1;
#if defined (_370)
if (strcasecmp (buf, arch_name[ARCH_370]) == 0)
{
i = ARCH_370;
}
#endif
#if defined (_390)
if (strcasecmp (buf, arch_name[ARCH_390]) == 0)
{
i = ARCH_390;
}
#endif
#if defined (_900)
if (0
|| strcasecmp (buf, arch_name[ARCH_900]) == 0
|| strcasecmp (buf, "ESAME") == 0
)
{
i = ARCH_900;
}
#endif
if (i < 0)
{
// "SR: archmode '%s' not supported"
WRMSG(HHC02008, "E", buf);
goto sr_error_exit;
}
sysblk.arch_mode = i;
sysblk.pcpu = 0;
sysblk.dummyregs.arch_mode = sysblk.arch_mode;
#if defined(OPTION_FISHIO)
ios_arch_mode = sysblk.arch_mode;
#endif
break;
case SR_SYS_MAINSIZE:
SR_READ_VALUE(file, len, &mainsize, sizeof(mainsize));
if (mainsize > sysblk.mainsize)
{
char buf1[20];
char buf2[20];
MSGBUF(buf1, "%dM", (U32)(mainsize / (1024*1024)));
MSGBUF(buf2, "%dM", (U32)(sysblk.mainsize / (1024*1024)));
// "SR: mismatch in '%s': '%s' found, '%s' expected"
WRMSG(HHC02009, "E", "mainsize", buf1, buf2);
goto sr_error_exit;
}
break;
case SR_SYS_MAINSTOR:
TRACE("SR: Restoring MAINSTOR...\n");
SR_READ_BUF(file, sysblk.mainstor, mainsize);
break;
case SR_SYS_SKEYSIZE:
SR_READ_VALUE(file, len, &len, sizeof(len));
if (len > (U32)(sysblk.mainsize/STORAGE_KEY_UNITSIZE))
{
char buf1[20];
char buf2[20];
MSGBUF(buf1, "%d", len);
MSGBUF(buf2, "%d", (U32)(sysblk.mainsize/STORAGE_KEY_UNITSIZE));
// "SR: mismatch in '%s': '%s' found, '%s' expected"
WRMSG(HHC02009, "E", "storkey size", buf1, buf2);
goto sr_error_exit;
}
break;
case SR_SYS_STORKEYS:
TRACE("SR: Restoring Storage Keys...\n");
SR_READ_BUF(file, sysblk.storkeys, len);
break;
case SR_SYS_XPNDSIZE:
SR_READ_VALUE(file, len, &xpndsize, sizeof(xpndsize));
if (xpndsize > sysblk.xpndsize)
{
char buf1[20];
char buf2[20];
MSGBUF(buf1, "%dM", (U32)(xpndsize / (256)));
MSGBUF(buf2, "%dM", sysblk.xpndsize / (256));
// "SR: mismatch in '%s': '%s' found, '%s' expected"
WRMSG(HHC02009, "E", "expand size", buf1, buf2);
goto sr_error_exit;
}
break;
case SR_SYS_XPNDSTOR:
TRACE("SR: Restoring Expanded Storage...\n");
SR_READ_BUF(file, sysblk.xpndstor, xpndsize * 4096);
break;
case SR_SYS_IPLDEV:
SR_READ_VALUE(file, len, &sysblk.ipldev, sizeof(sysblk.ipldev));
break;
case SR_SYS_IPLCPU:
SR_READ_VALUE(file, len, &sysblk.iplcpu, sizeof(sysblk.iplcpu));
break;
case SR_SYS_MBO:
SR_READ_VALUE(file, len, &sysblk.mbo, sizeof(sysblk.mbo));
break;
case SR_SYS_MBK:
SR_READ_VALUE(file, len, &sysblk.mbk, sizeof(sysblk.mbk));
break;
case SR_SYS_MBM:
SR_READ_VALUE(file, len, &sysblk.mbm, sizeof(sysblk.mbm));
break;
case SR_SYS_MBD:
SR_READ_VALUE(file, len, &sysblk.mbd, sizeof(sysblk.mbd));
break;
case SR_SYS_IOPENDING_LCSS:
SR_READ_VALUE(file,len,&lcss,sizeof(lcss));
break;
case SR_SYS_IOPENDING:
SR_READ_VALUE(file, len, &hw, sizeof(hw));
dev = find_device_by_devnum(lcss,hw);
if (dev == NULL) break;
if (ioq == NULL)
sysblk.iointq = &dev->ioint;
else
ioq->next = &dev->ioint;
ioq = &dev->ioint;
dev = NULL;
lcss = 0;
break;
case SR_SYS_PCIPENDING_LCSS:
SR_READ_VALUE(file,len,&lcss,sizeof(lcss));
break;
case SR_SYS_PCIPENDING:
SR_READ_VALUE(file, len, &hw, sizeof(hw));
dev = find_device_by_devnum(lcss,hw);
if (dev == NULL) break;
if (ioq == NULL)
sysblk.iointq = &dev->pciioint;
else
ioq->next = &dev->pciioint;
ioq = &dev->pciioint;
dev = NULL;
lcss = 0;
break;
case SR_SYS_ATTNPENDING_LCSS:
SR_READ_VALUE(file,len,&lcss,sizeof(lcss));
break;
case SR_SYS_ATTNPENDING:
SR_READ_VALUE(file, len, &hw, sizeof(hw));
dev = find_device_by_devnum(lcss,hw);
if (dev == NULL) break;
if (ioq == NULL)
sysblk.iointq = &dev->attnioint;
else
ioq->next = &dev->attnioint;
ioq = &dev->attnioint;
dev = NULL;
lcss = 0;
break;
case SR_SYS_CHP_RESET_0:
case SR_SYS_CHP_RESET_1:
case SR_SYS_CHP_RESET_2:
case SR_SYS_CHP_RESET_3:
case SR_SYS_CHP_RESET_4:
case SR_SYS_CHP_RESET_5:
case SR_SYS_CHP_RESET_6:
case SR_SYS_CHP_RESET_7:
i = key - SR_SYS_CHP_RESET;
SR_READ_VALUE(file, len, &sysblk.chp_reset[i], sizeof(sysblk.chp_reset[0]));
break;
case SR_SYS_SERVPARM:
SR_READ_VALUE(file, len, &sysblk.servparm, sizeof(sysblk.servparm));
break;
case SR_SYS_SIGINTREQ:
SR_READ_VALUE(file, len, &rc, sizeof(rc));
sysblk.sigintreq = rc;
break;
case SR_SYS_LOADPARM:
SR_READ_STRING(file, buf, len);
set_loadparm ((char *)buf);
break;
case SR_SYS_SERVC:
TRACE("SR: Restoring Service Console State...\n");
rc = servc_hresume(file);
if (rc < 0) goto sr_error_exit;
break;
case SR_SYS_CLOCK:
TRACE("SR: Restoring Clock State...\n");
rc = clock_hresume(file);
if (rc < 0) goto sr_error_exit;
break;
case SR_CPU:
SR_READ_VALUE(file, len, &i, sizeof(i));
TRACE("SR: Restoring CPU %d Data...\n", i);
if (i >= sysblk.maxcpu)
{
// "SR: processor CP%02X exceeds max allowed CP%02X"
WRMSG(HHC02010, "E", i, sysblk.maxcpu-1);
goto sr_error_exit;
}
OBTAIN_INTLOCK(NULL);
if (IS_CPU_ONLINE(i))
{
RELEASE_INTLOCK(NULL);
// "SR: processor %s%02X already configured"
WRMSG(HHC02011, "E", PTYPSTR(i), i);
goto sr_error_exit;
}
rc = configure_cpu(i);
RELEASE_INTLOCK(NULL);
if (rc < 0)
{
// "SR: processor %s%02X unable to configure online"
WRMSG(HHC02012, "E", PTYPSTR(i), i);
goto sr_error_exit;
}
regs = sysblk.regs[i];
break;
case SR_CPU_PX:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, ®s->px, sizeof(regs->px));
break;
case SR_CPU_PSW:
SR_NULL_REGS_CHECK(regs);
if (len != 8 && len != 16)
{
// "SR: processor %s%02X invalid psw length %d"
WRMSG(HHC02013, "E", PTYPSTR(regs->cpuad), regs->cpuad, len);
goto sr_error_exit;
}
memset(buf, 0, 16);
SR_READ_BUF(file, buf, len);
switch (regs->arch_mode) {
#if defined (_370)
case ARCH_370:
len = 8;
rc = s370_load_psw(regs, (BYTE *)&buf);
break;
#endif
#if defined (_390)
case ARCH_390:
len = 8;
rc = s390_load_psw(regs, (BYTE *)&buf);
break;
#endif
#if defined (_900)
case ARCH_900:
len = 16;
rc = z900_load_psw(regs, (BYTE *)&buf);
break;
#endif
} /* switch (regs->arch_mode) */
if (rc != 0 && memcmp(buf, zeros, len))
{
// "SR: processor %s%02X error loading psw, rc %d"
WRMSG(HHC02014, "E", PTYPSTR(regs->cpuad), regs->cpuad, rc);
goto sr_error_exit;
}
break;
case SR_CPU_GR_0:
case SR_CPU_GR_1:
case SR_CPU_GR_2:
case SR_CPU_GR_3:
case SR_CPU_GR_4:
case SR_CPU_GR_5:
case SR_CPU_GR_6:
case SR_CPU_GR_7:
case SR_CPU_GR_8:
case SR_CPU_GR_9:
case SR_CPU_GR_10:
case SR_CPU_GR_11:
case SR_CPU_GR_12:
case SR_CPU_GR_13:
case SR_CPU_GR_14:
case SR_CPU_GR_15:
SR_NULL_REGS_CHECK(regs);
i = key - SR_CPU_GR;
SR_READ_VALUE(file, len, ®s->gr[i], sizeof(regs->gr[0]));
break;
case SR_CPU_CR_0:
case SR_CPU_CR_1:
case SR_CPU_CR_2:
case SR_CPU_CR_3:
case SR_CPU_CR_4:
case SR_CPU_CR_5:
case SR_CPU_CR_6:
case SR_CPU_CR_7:
case SR_CPU_CR_8:
case SR_CPU_CR_9:
case SR_CPU_CR_10:
case SR_CPU_CR_11:
case SR_CPU_CR_12:
case SR_CPU_CR_13:
case SR_CPU_CR_14:
case SR_CPU_CR_15:
SR_NULL_REGS_CHECK(regs);
i = key - SR_CPU_CR;
SR_READ_VALUE(file, len, ®s->CR(i), sizeof(regs->CR(0)));
break;
case SR_CPU_AR_0:
case SR_CPU_AR_1:
case SR_CPU_AR_2:
case SR_CPU_AR_3:
case SR_CPU_AR_4:
case SR_CPU_AR_5:
case SR_CPU_AR_6:
case SR_CPU_AR_7:
case SR_CPU_AR_8:
case SR_CPU_AR_9:
case SR_CPU_AR_10:
case SR_CPU_AR_11:
case SR_CPU_AR_12:
case SR_CPU_AR_13:
case SR_CPU_AR_14:
case SR_CPU_AR_15:
SR_NULL_REGS_CHECK(regs);
i = key - SR_CPU_AR;
SR_READ_VALUE(file, len, ®s->ar[i], sizeof(regs->ar[0]));
break;
case SR_CPU_FPR_0:
case SR_CPU_FPR_1:
case SR_CPU_FPR_2:
case SR_CPU_FPR_3:
case SR_CPU_FPR_4:
case SR_CPU_FPR_5:
case SR_CPU_FPR_6:
case SR_CPU_FPR_7:
case SR_CPU_FPR_8:
case SR_CPU_FPR_9:
case SR_CPU_FPR_10:
case SR_CPU_FPR_11:
case SR_CPU_FPR_12:
case SR_CPU_FPR_13:
case SR_CPU_FPR_14:
case SR_CPU_FPR_15:
case SR_CPU_FPR_16:
case SR_CPU_FPR_17:
case SR_CPU_FPR_18:
case SR_CPU_FPR_19:
case SR_CPU_FPR_20:
case SR_CPU_FPR_21:
case SR_CPU_FPR_22:
case SR_CPU_FPR_23:
case SR_CPU_FPR_24:
case SR_CPU_FPR_25:
case SR_CPU_FPR_26:
case SR_CPU_FPR_27:
case SR_CPU_FPR_28:
case SR_CPU_FPR_29:
case SR_CPU_FPR_30:
case SR_CPU_FPR_31:
SR_NULL_REGS_CHECK(regs);
i = key - SR_CPU_FPR;
SR_READ_VALUE(file, len, ®s->fpr[i], sizeof(regs->fpr[0]));
break;
case SR_CPU_FPC:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, ®s->fpc, sizeof(regs->fpc));
break;
case SR_CPU_DXC:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, ®s->dxc, sizeof(regs->dxc));
break;
case SR_CPU_MC:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, ®s->mc, sizeof(regs->mc));
break;
case SR_CPU_EA:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, ®s->ea, sizeof(regs->ea));
break;
case SR_CPU_PTIMER:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, &dreg, sizeof(S64));
set_cpu_timer(regs, dreg);
break;
case SR_CPU_CLKC:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, ®s->clkc, sizeof(regs->clkc));
break;
case SR_CPU_CHANSET:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, ®s->chanset, sizeof(regs->chanset));
break;
case SR_CPU_TODPR:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, ®s->todpr, sizeof(regs->todpr));
break;
case SR_CPU_MONCLASS:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, ®s->monclass, sizeof(regs->monclass));
break;
case SR_CPU_EXCARID:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, ®s->excarid, sizeof(regs->excarid));
break;
case SR_CPU_BEAR:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, ®s->bear, sizeof(regs->bear));
break;
case SR_CPU_OPNDRID:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, ®s->opndrid, sizeof(regs->opndrid));
break;
case SR_CPU_CHECKSTOP:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, &rc, sizeof(rc));
regs->checkstop = rc;
break;
case SR_CPU_HOSTINT:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, &rc, sizeof(rc));
regs->hostint = rc;
break;
case SR_CPU_LOADSTATE:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, &rc, sizeof(rc));
regs->loadstate = rc;
break;
case SR_CPU_INVALIDATE:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, &rc, sizeof(rc));
regs->invalidate = rc;
break;
case SR_CPU_SIGPRESET:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, &rc, sizeof(rc));
regs->sigpreset = rc;
break;
case SR_CPU_SIGPIRESET:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, &rc, sizeof(rc));
regs->sigpireset = rc;
break;
case SR_CPU_INTS_STATE:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, ®s->ints_state, sizeof(regs->ints_state));
/* Force CPU to examine the interrupt state */
ON_IC_INTERRUPT(regs);
break;
case SR_CPU_INTS_MASK:
SR_NULL_REGS_CHECK(regs);
SR_READ_VALUE(file, len, ®s->ints_mask, sizeof(regs->ints_mask));
break;
case SR_CPU_MALFCPU_0:
case SR_CPU_MALFCPU_1:
case SR_CPU_MALFCPU_2:
case SR_CPU_MALFCPU_3:
case SR_CPU_MALFCPU_4:
case SR_CPU_MALFCPU_5:
case SR_CPU_MALFCPU_6:
case SR_CPU_MALFCPU_7:
case SR_CPU_MALFCPU_8:
case SR_CPU_MALFCPU_9:
case SR_CPU_MALFCPU_10:
case SR_CPU_MALFCPU_11:
case SR_CPU_MALFCPU_12:
case SR_CPU_MALFCPU_13:
case SR_CPU_MALFCPU_14:
case SR_CPU_MALFCPU_15:
case SR_CPU_MALFCPU_16:
case SR_CPU_MALFCPU_17:
case SR_CPU_MALFCPU_18:
case SR_CPU_MALFCPU_19:
case SR_CPU_MALFCPU_20:
case SR_CPU_MALFCPU_21:
case SR_CPU_MALFCPU_22:
case SR_CPU_MALFCPU_23:
case SR_CPU_MALFCPU_24:
case SR_CPU_MALFCPU_25:
case SR_CPU_MALFCPU_26:
case SR_CPU_MALFCPU_27:
case SR_CPU_MALFCPU_28:
case SR_CPU_MALFCPU_29:
case SR_CPU_MALFCPU_30:
case SR_CPU_MALFCPU_31:
SR_NULL_REGS_CHECK(regs);
i = key - SR_CPU_MALFCPU;
if (i < sysblk.maxcpu)
SR_READ_VALUE(file, len, ®s->malfcpu[i], sizeof(regs->malfcpu[0]));
break;
case SR_CPU_EMERCPU_0:
case SR_CPU_EMERCPU_1:
case SR_CPU_EMERCPU_2:
case SR_CPU_EMERCPU_3:
case SR_CPU_EMERCPU_4:
case SR_CPU_EMERCPU_5:
case SR_CPU_EMERCPU_6:
case SR_CPU_EMERCPU_7:
case SR_CPU_EMERCPU_8:
case SR_CPU_EMERCPU_9:
case SR_CPU_EMERCPU_10:
case SR_CPU_EMERCPU_11:
case SR_CPU_EMERCPU_12:
case SR_CPU_EMERCPU_13:
case SR_CPU_EMERCPU_14:
case SR_CPU_EMERCPU_15:
case SR_CPU_EMERCPU_16:
case SR_CPU_EMERCPU_17:
case SR_CPU_EMERCPU_18:
case SR_CPU_EMERCPU_19:
case SR_CPU_EMERCPU_20:
case SR_CPU_EMERCPU_21:
case SR_CPU_EMERCPU_22:
case SR_CPU_EMERCPU_23:
case SR_CPU_EMERCPU_24:
case SR_CPU_EMERCPU_25:
case SR_CPU_EMERCPU_26:
case SR_CPU_EMERCPU_27:
case SR_CPU_EMERCPU_28:
case SR_CPU_EMERCPU_29:
case SR_CPU_EMERCPU_30:
case SR_CPU_EMERCPU_31:
SR_NULL_REGS_CHECK(regs);
i = key - SR_CPU_EMERCPU;
if (i < sysblk.maxcpu)
SR_READ_VALUE(file, len, ®s->emercpu[i], sizeof(regs->emercpu[0]));
break;
case SR_DEV:
SR_READ_VALUE(file, len, &devnum, sizeof(devnum));
TRACE("SR: Restoring Device %4.4X...\n", devnum);
lcss=0;
break;
case SR_DEV_LCSS:
SR_READ_VALUE(file, len, &lcss, sizeof(U16));
break;
case SR_DEV_ARGC:
SR_READ_VALUE(file, len, &devargc, sizeof(devargc));
if (devargc > 16) devargc = 16;
for (i = 0; i < devargc; i++) devargv[i] = NULL;
devargx = 0;
break;
case SR_DEV_ARGV:
SR_READ_STRING(file, buf, len);
if (devargx < devargc) devargv[devargx++] = strdup(buf);
break;
case SR_DEV_TYPNAME:
SR_READ_STRING(file, buf, len);
dev = find_device_by_devnum(lcss,devnum);
if (dev == NULL)
{
if (attach_device (lcss, devnum, buf, devargc, devargv))
{
// "SR: %04X: device initialization failed"
WRMSG(HHC02015, "E", devnum);
}
}
else if (strcmp(dev->typname, buf))
{
// "SR: %04X: device type mismatch; '%s' found, '%s' expected"
WRMSG(HHC02016, "W", devnum, buf, dev->typname);
dev = NULL;
}
for (i = 0; i < devargx; i++)
{
if (devargv[i]) free(devargv[i]);
devargv[i] = NULL;
}
devnum = devargc = devargx = 0;
break;
case SR_DEV_ORB:
SR_SKIP_NULL_DEV(dev, file, len);
if (len != sizeof(ORB))
{
// "SR: %04X: '%s' size mismatch: %d found, %d expected"
WRMSG(HHC02017, "E", dev->devnum, "ORB", len, (int)sizeof(ORB));
goto sr_error_exit;
}
SR_READ_BUF(file, &dev->orb, len);
break;
case SR_DEV_PMCW:
SR_SKIP_NULL_DEV(dev, file, len);
if (len != sizeof(PMCW))
{
// "SR: %04X: '%s' size mismatch: %d found, %d expected"
WRMSG(HHC02017, "E", dev->devnum, "PMCW", len, (int)sizeof(PMCW));
goto sr_error_exit;
}
SR_READ_BUF(file, &dev->pmcw, len);
break;
case SR_DEV_SCSW:
SR_SKIP_NULL_DEV(dev, file, len);
if (len != sizeof(SCSW))
{
// "SR: %04X: '%s' size mismatch: %d found, %d expected"
WRMSG(HHC02017, "E", dev->devnum, "SCSW", len, (int)sizeof(SCSW));
goto sr_error_exit;
}
SR_READ_BUF(file, &dev->scsw, len);
break;
case SR_DEV_PCISCSW:
SR_SKIP_NULL_DEV(dev, file, len);
if (len != sizeof(SCSW))
{
// "SR: %04X: '%s' size mismatch: %d found, %d expected"
WRMSG(HHC02017, "E", dev->devnum, "PCI SCSW", len, (int)sizeof(SCSW));
goto sr_error_exit;
}
SR_READ_BUF(file, &dev->pciscsw, len);
break;
case SR_DEV_ATTNSCSW:
SR_SKIP_NULL_DEV(dev, file, len);
if (len != sizeof(SCSW))
{
// "SR: %04X: '%s' size mismatch: %d found, %d expected"
WRMSG(HHC02017, "E", dev->devnum, "ATTN SCSW", len, (int)sizeof(SCSW));
goto sr_error_exit;
}
SR_READ_BUF(file, &dev->attnscsw, len);
break;
case SR_DEV_CSW:
SR_SKIP_NULL_DEV(dev, file, len);
if (len != 8)
{
// "SR: %04X: '%s' size mismatch: %d found, %d expected"
WRMSG(HHC02017, "E", dev->devnum, "CSW", len, 8);
goto sr_error_exit;
}
SR_READ_BUF(file, &dev->csw, len);
break;
case SR_DEV_PCICSW:
SR_SKIP_NULL_DEV(dev, file, len);
if (len != 8)
{
// "SR: %04X: '%s' size mismatch: %d found, %d expected"
WRMSG(HHC02017, "E", dev->devnum, "PCI CSW", len, 8);
goto sr_error_exit;
}
SR_READ_BUF(file, &dev->pcicsw, len);
break;
case SR_DEV_ATTNCSW:
SR_SKIP_NULL_DEV(dev, file, len);
if (len != 8)
{
// "SR: %04X: '%s' size mismatch: %d found, %d expected"
WRMSG(HHC02017, "E", dev->devnum, "ATTN CSW", len, 8);
goto sr_error_exit;
}
SR_READ_BUF(file, &dev->attncsw, len);
break;
case SR_DEV_ESW:
SR_SKIP_NULL_DEV(dev, file, len);
if (len != sizeof(ESW))
{
// "SR: %04X: '%s' size mismatch: %d found, %d expected"
WRMSG(HHC02017, "E", dev->devnum, "ESW", len, (int)sizeof(ESW));
goto sr_error_exit;
}
SR_READ_BUF(file, &dev->esw, len);
break;
case SR_DEV_ECW:
SR_SKIP_NULL_DEV(dev, file, len);
if (len != 32)
{
// "SR: %04X: '%s' size mismatch: %d found, %d expected"
WRMSG(HHC02017, "E", dev->devnum, "ECW", len, 32);
goto sr_error_exit;
}
SR_READ_BUF(file, &dev->ecw, len);
break;
case SR_DEV_SENSE:
SR_SKIP_NULL_DEV(dev, file, len);
if (len != 32)
{
// "SR: %04X: '%s' size mismatch: %d found, %d expected"
WRMSG(HHC02017, "E", dev->devnum, "Sense", len, 32);
goto sr_error_exit;
}
SR_READ_BUF(file, &dev->ecw, len);
break;
case SR_DEV_PGSTAT:
SR_SKIP_NULL_DEV(dev, file, len);
SR_READ_VALUE(file, len, &dev->pgstat, sizeof(dev->pgstat));
break;
case SR_DEV_PGID:
SR_SKIP_NULL_DEV(dev, file, len);
if (len != 11)
{
// "SR: %04X: '%s' size mismatch: %d found, %d expected"
WRMSG(HHC02017, "E", dev->devnum, "PGID", len, 11);
goto sr_error_exit;
}
SR_READ_BUF(file, &dev->pgid, len);
break;
/* By Adrian - SR_DEV_DRVPWD */
case SR_DEV_DRVPWD:
SR_SKIP_NULL_DEV(dev, file, len);
if (len != 11)
{
// "SR: %04X: '%s' size mismatch: %d found, %d expected"
WRMSG(HHC02017, "E", dev->devnum, "DRVPWD", len, 11);
goto sr_error_exit;
}
SR_READ_BUF(file, &dev->drvpwd, len);
break;
case SR_DEV_BUSY:
SR_SKIP_NULL_DEV(dev, file, len);
SR_READ_VALUE(file, len, &rc, sizeof(rc));
dev->busy = rc;
break;
case SR_DEV_RESERVED:
SR_SKIP_NULL_DEV(dev, file, len);
SR_READ_VALUE(file, len, &rc, sizeof(rc));
dev->reserved = rc;
break;
case SR_DEV_SUSPENDED:
SR_SKIP_NULL_DEV(dev, file, len);
SR_READ_VALUE(file, len, &rc, sizeof(rc));
dev->suspended = rc;
break;
case SR_DEV_PENDING:
SR_SKIP_NULL_DEV(dev, file, len);
SR_READ_VALUE(file, len, &rc, sizeof(rc));
dev->pending = rc;
QUEUE_IO_INTERRUPT(&dev->ioint);
break;
case SR_DEV_PCIPENDING:
SR_SKIP_NULL_DEV(dev, file, len);
SR_READ_VALUE(file, len, &rc, sizeof(rc));
dev->pcipending = rc;
QUEUE_IO_INTERRUPT(&dev->pciioint);
break;
case SR_DEV_ATTNPENDING:
SR_SKIP_NULL_DEV(dev, file, len);
SR_READ_VALUE(file, len, &rc, sizeof(rc));
dev->attnpending = rc;
QUEUE_IO_INTERRUPT(&dev->attnioint);
break;
case SR_DEV_STARTPENDING:
SR_SKIP_NULL_DEV(dev, file, len);
SR_READ_VALUE(file, len, &rc, sizeof(rc));
dev->startpending = rc;
break;
case SR_DEV_CRWPENDING:
SR_SKIP_NULL_DEV(dev, file, len);
SR_READ_VALUE(file, len, &rc, sizeof(rc));
dev->crwpending = rc;
break;
case SR_DEV_CCWADDR:
SR_SKIP_NULL_DEV(dev, file, len);
SR_READ_VALUE(file, len, &dev->ccwaddr, sizeof(dev->ccwaddr));
break;
case SR_DEV_IDAPMASK:
SR_SKIP_NULL_DEV(dev, file, len);
SR_READ_VALUE(file, len, &dev->idapmask, sizeof(dev->idapmask));
break;
case SR_DEV_IDAWFMT:
SR_SKIP_NULL_DEV(dev, file, len);
SR_READ_VALUE(file, len, &dev->idawfmt, sizeof(dev->idawfmt));
break;
case SR_DEV_CCWFMT:
SR_SKIP_NULL_DEV(dev, file, len);
SR_READ_VALUE(file, len, &dev->ccwfmt, sizeof(dev->ccwfmt));
break;
case SR_DEV_CCWKEY:
SR_SKIP_NULL_DEV(dev, file, len);
SR_READ_VALUE(file, len, &dev->ccwkey, sizeof(dev->ccwkey));
break;
/* This is the trigger to call the device dependent resume routine */
case SR_DEV_DEVTYPE:
SR_SKIP_NULL_DEV(dev, file, len);
SR_READ_VALUE(file, len, &hw, sizeof(hw));
if (hw != dev->devtype)
{
char buf1[20];
char buf2[20];
MSGBUF(buf1, "%04X", hw);
MSGBUF(buf2, "%04X", dev->devtype);
// "SR: %04X: device type mismatch; '%s' found, '%s' expected"
WRMSG(HHC02016, "E", dev->devnum, buf1, buf2);
goto sr_error_exit;
}
if (dev->hnd->hresume)
{
rc = (dev->hnd->hresume) (dev, file);
if (rc < 0) goto sr_error_exit;
}
break;
default:
if ((key & SR_KEY_ID_MASK) != SR_KEY_ID)
{
// "SR: invalid key %8.8X"
WRMSG(HHC02018, "E", key);
goto sr_error_exit;
}
SR_READ_SKIP(file, len);
break;
} /* switch (key) */
} /* while (key != SR_EOF) */
TRACE("SR: Resume File Processing Complete...\n");
TRACE("SR: Resuming Devices...\n");
/* For all suspended devices, resume the `suspended' state */
for (dev = sysblk.firstdev; dev; dev = dev->nextdev)
{
if (dev->suspended && (dev->pmcw.flag5 & PMCW5_V))
{
dev->resumesuspended=1;
switch (sysblk.arch_mode) {
#if defined(_370)
case ARCH_370:
rc = create_thread (&dev->tid, DETACHED,
s370_execute_ccw_chain, dev, "device thread");
break;
#endif
#if defined(_390)
case ARCH_390:
rc = create_thread (&dev->tid, DETACHED,
s390_execute_ccw_chain, dev, "device thread");
break;
#endif
#if defined(_900)
case ARCH_900:
rc = create_thread (&dev->tid, DETACHED,
z900_execute_ccw_chain, dev, "device thread");
break;
#endif
} /* switch (sysblk.arch_mode) */
if (rc != 0)
{
// "Error in function create_thread(): %s"
WRMSG(HHC00102, "E", strerror(rc));
goto sr_error_exit;
}
} /* If suspended device */
} /* For each device */
/* Indicate crw pending for any new devices */
#if defined(_370)
if (sysblk.arch_mode != ARCH_370)
#endif
machine_check_crwpend();
/* Start the CPUs */
TRACE("SR: Resuming CPUs...\n");
OBTAIN_INTLOCK(NULL);
ON_IC_IOPENDING;
for (i = 0; i < sysblk.maxcpu; i++)
if (IS_CPU_ONLINE(i) && (started_mask & CPU_BIT(i)))
{
sysblk.regs[i]->opinterv = 0;
sysblk.regs[i]->cpustate = CPUSTATE_STARTED;
sysblk.regs[i]->checkstop = 0;
WAKEUP_CPU(sysblk.regs[i]);
}
RELEASE_INTLOCK(NULL);
TRACE("SR: Resume Complete; System Resumed.\n");
return 0;
sr_null_regs_exit:
// "SR: CPU key %8.8X found but no active CPU"
WRMSG(HHC02019, "E", key);
goto sr_error_exit;
sr_error_exit:
// "SR: error processing file '%s'"
WRMSG(HHC02004, "E", fn);
SR_CLOSE (file);
return -1;
}
/*-------------------------------------------------------------------*/
int ARCH_DEP(load_ipl) (U16 lcss, U16 devnum, int cpu, int clear)
{
REGS *regs; /* -> Regs */
DEVBLK *dev; /* -> Device control block */
int i; /* Array subscript */
BYTE unitstat; /* IPL device unit status */
BYTE chanstat; /* IPL device channel status */
/* Get started */
if (ARCH_DEP(common_load_begin) (cpu, clear) != 0)
return -1;
/* The actual IPL proper starts here... */
regs = sysblk.regs[cpu]; /* Point to IPL CPU's registers */
/* Point to the device block for the IPL device */
dev = find_device_by_devnum (lcss,devnum);
if (dev == NULL)
{
logmsg (_("HHCCP027E Device %4.4X not in configuration%s\n"),
devnum,
(sysblk.arch_mode == ARCH_370 ?
" or not conneceted to channelset" : ""));
HDC1(debug_cpu_state, regs);
return -1;
}
#if defined(OPTION_IPLPARM)
if(sysblk.haveiplparm)
{
for(i=0;i<16;i++)
{
regs->GR_L(i)=fetch_fw(&sysblk.iplparmstring[i*4]);
}
sysblk.haveiplparm=0;
}
#endif
/* Set Main Storage Reference and Update bits */
STORAGE_KEY(regs->PX, regs) |= (STORKEY_REF | STORKEY_CHANGE);
sysblk.main_clear = sysblk.xpnd_clear = 0;
/* Build the IPL CCW at location 0 */
regs->psa->iplpsw[0] = 0x02; /* CCW command = Read */
regs->psa->iplpsw[1] = 0; /* Data address = zero */
regs->psa->iplpsw[2] = 0;
regs->psa->iplpsw[3] = 0;
regs->psa->iplpsw[4] = CCW_FLAGS_CC | CCW_FLAGS_SLI;
/* CCW flags */
regs->psa->iplpsw[5] = 0; /* Reserved byte */
regs->psa->iplpsw[6] = 0; /* Byte count = 24 */
regs->psa->iplpsw[7] = 24;
/* Enable the subchannel for the IPL device */
dev->pmcw.flag5 |= PMCW5_E;
/* Build the operation request block */ /*@IWZ*/
memset (&dev->orb, 0, sizeof(ORB)); /*@IWZ*/
dev->busy = 1;
RELEASE_INTLOCK(NULL);
/* Execute the IPL channel program */
ARCH_DEP(execute_ccw_chain) (dev);
OBTAIN_INTLOCK(NULL);
/* Clear the interrupt pending and device busy conditions */
obtain_lock (&sysblk.iointqlk);
DEQUEUE_IO_INTERRUPT_QLOCKED(&dev->ioint);
DEQUEUE_IO_INTERRUPT_QLOCKED(&dev->pciioint);
DEQUEUE_IO_INTERRUPT_QLOCKED(&dev->attnioint);
release_lock(&sysblk.iointqlk);
dev->busy = 0;
dev->scsw.flag2 = 0;
dev->scsw.flag3 = 0;
/* Check that load completed normally */
#ifdef FEATURE_S370_CHANNEL
unitstat = dev->csw[4];
chanstat = dev->csw[5];
#endif /*FEATURE_S370_CHANNEL*/
#ifdef FEATURE_CHANNEL_SUBSYSTEM
unitstat = dev->scsw.unitstat;
chanstat = dev->scsw.chanstat;
#endif /*FEATURE_CHANNEL_SUBSYSTEM*/
if (unitstat != (CSW_CE | CSW_DE) || chanstat != 0) {
logmsg (_("HHCCP029E %s mode IPL failed: CSW status=%2.2X%2.2X\n"
" Sense="),
get_arch_mode_string(regs), unitstat, chanstat);
for (i=0; i < (int)dev->numsense; i++)
{
logmsg ("%2.2X", dev->sense[i]);
if ((i & 3) == 3) logmsg(" ");
}
logmsg ("\n");
HDC1(debug_cpu_state, regs);
return -1;
}
#ifdef FEATURE_S370_CHANNEL
/* Test the EC mode bit in the IPL PSW */
if (regs->psa->iplpsw[1] & 0x08) {
/* In EC mode, store device address at locations 184-187 */
STORE_FW(regs->psa->ioid, dev->devnum);
} else {
/* In BC mode, store device address at locations 2-3 */
STORE_HW(regs->psa->iplpsw + 2, dev->devnum);
}
#endif /*FEATURE_S370_CHANNEL*/
#ifdef FEATURE_CHANNEL_SUBSYSTEM
/* Set LPUM */
dev->pmcw.lpum = 0x80;
STORE_FW(regs->psa->ioid, (dev->ssid<<16)|dev->subchan);
/* Store zeroes at locations 188-191 */
memset (regs->psa->ioparm, 0, 4);
#endif /*FEATURE_CHANNEL_SUBSYSTEM*/
/* Save IPL device number, cpu number and lcss */
sysblk.ipldev = devnum;
sysblk.iplcpu = regs->cpuad;
sysblk.ipllcss = lcss;
/* Finish up... */
return ARCH_DEP(common_load_finish) (regs);
} /* end function load_ipl */