/************************************************************************************************** * @fn MRFI_Init * * @brief Initialize MRFI. * * @param none * * @return none ************************************************************************************************** */ void MRFI_Init(void) { /* Configure Output lines */ MRFI_CONFIG_RESETN_PIN_AS_OUTPUT(); MRFI_CONFIG_VREG_EN_PIN_AS_OUTPUT(); /* Configure Input lines */ MRFI_CONFIG_TX_FRAME_DONE_AS_INPUT(); MRFI_CONFIG_FIFO_AS_INPUT(); MRFI_CONFIG_FIFOP_AS_INPUT(); /* Initialize SPI */ mrfiSpiInit(); /* Power up the radio chip */ Mrfi_TurnOnRadioPower(); /* Confirm that we are talking to the right hardware */ MRFI_ASSERT(mrfiSpiReadReg(CHIPID) == MRFI_RADIO_PARTNUM); /* Random Number Generator: * The seed value for the randon number generator logic * is derived from the radio. */ /* Set radio in rx mode, but with symbol search disabled. Used for RSSI * measurments or when we don't care about the received frames. */ mrfiSpiWriteReg(FRMCTRL0, FRMCTRL0_RESET_VALUE | RX_MODE_RSSI_ONLY); /* Turn on the receiver */ mrfiSpiCmdStrobe(SRXON); /* * Wait for RSSI to be valid. RANDOM command strobe can be used * to generate random number only after this. */ MRFI_RSSI_VALID_WAIT(); /* Get random byte from the radio */ mrfiRndSeed = mrfiSpiRandomByte(); /* * The seed value must not be zero. If it is, the pseudo random sequence * will be always be zero. There is an extremely small chance this seed could * randomly be zero (more likely some type of hardware problem would cause * this). If it is zero, initialize it to something. */ if(mrfiRndSeed == 0) { mrfiRndSeed = 0x80; } /* Random number initialization is done. Turn the radio off */ Mrfi_TurnOffRadioPower(); /* Initial radio state is - OFF state */ mrfiRadioState = MRFI_RADIO_STATE_OFF; /********************************************************************************** * Compute reply delay scalar * * The IEEE radio has a fixed data rate of 250 Kbps. Data rate inference * from radio regsiters is not necessary for this radio. * * The maximum delay needed depends on the MAX_APP_PAYLOAD parameter. Figure * out how many bits that will be when overhead is included. Bits/bits-per-second * is seconds to transmit (or receive) the maximum frame. We multiply this number * by 1000 to find the time in milliseconds. We then additionally multiply by * 10 so we can add 5 and divide by 10 later, thus rounding up to the number of * milliseconds. This last won't matter for slow transmissions but for faster ones * we want to err on the side of being conservative and making sure the radio is on * to receive the reply. The semaphore monitor will shut it down. The delay adds in * a fudge factor that includes processing time on peer plus lags in Rx and processing * time on receiver's side. * * ********************************************************************************** */ #define PLATFORM_FACTOR_CONSTANT 2 #define PHY_PREAMBLE_SYNC_BYTES 8 { uint32_t bits, dataRate = 250000; bits = ((uint32_t)((PHY_PREAMBLE_SYNC_BYTES + MRFI_MAX_FRAME_SIZE)*8))*10000; /* processing on the peer + the Tx/Rx time plus more */ sReplyDelayScalar = PLATFORM_FACTOR_CONSTANT + (((bits/dataRate)+5)/10); } /* Random delay: This prevents devices on the same power source from repeated * transmit collisions on power up. */ Mrfi_RandomBackoffDelay(); BSP_ENABLE_INTERRUPTS(); }
/************************************************************************************************** * @fn MRFI_Init * * @brief Initialize MRFI. * * @param none * * @return none ************************************************************************************************** */ void MRFI_Init(void) { /* ------------------------------------------------------------------ * Run-time integrity checks * --------------------------- */ memset(&mrfiIncomingPacket, 0x0, sizeof(mrfiIncomingPacket)); /* verify the correct radio is installed */ MRFI_ASSERT( CHIPID == MRFI_RADIO_PARTNUM ); /* wrong radio */ MRFI_ASSERT( CHVER >= MRFI_RADIO_MIN_VERSION ); /* obsolete radio version */ /* ------------------------------------------------------------------ * Configure IO ports * --------------------------- */ #if defined(MRFI_PA_LNA_ENABLED) && defined(BSP_BOARD_SRF04EB) MRFI_BOARD_PA_LNA_CONFIG_PORTS(); MRFI_BOARD_PA_LNA_HGM(); #endif /* ------------------------------------------------------------------ * Configure clock to use XOSC * ----------------------------- */ SLEEPCMD &= ~OSC_PD; /* turn on 16MHz RC and 32MHz XOSC */ while (!(SLEEPSTA & XOSC_STB)); /* wait for 32MHz XOSC stable */ asm("NOP"); /* chip bug workaround */ { uint16_t i; /* Require 63us delay for all revs */ for (i=0; i<504; i++) { asm("NOP"); } } CLKCONCMD = (0x00 | OSC_32KHZ); /* 32MHz XOSC */ while (CLKCONSTA != (0x00 | OSC_32KHZ)); SLEEPCMD |= OSC_PD; /* turn off 16MHz RC */ /* Configure radio registers that should be different from reset values. */ Mrfi_RadioRegConfig(); /* ------------------------------------------------------------------ * Variable Initialization * ------------------------- */ #ifdef MRFI_ASSERTS_ARE_ON PAN_ID0 = 0xFF; PAN_ID1 = 0xFF; #endif /* ------------------------------------------------------------------ * Initialize Random Seed Value * ------------------------------- */ /* * Set radio for infinite reception. Once radio reaches this state, * it will stay in receive mode regardless RF activity. */ FRMCTRL0 = (FRMCTRL0 & ~RX_MODE_MASK) | RX_MODE_INFINITE_RX; /* turn on the receiver */ RFST = ISRXON; /* Wait for RSSI to be valid. Once valid, radio is stable and random bits * can be read. */ MRFI_RSSI_VALID_WAIT(); /* put 16 random bits into the seed value */ { uint16_t rndSeed; uint8_t i; rndSeed = 0; for(i=0; i<16; i++) { /* read random bit to populate the random seed */ rndSeed = (rndSeed << 1) | (RFRND & 0x01); } /* * The seed value must not be zero. If it is, the pseudo random sequence will be always be zero. * There is an extremely small chance this seed could randomly be zero (more likely some type of * hardware problem would cause this). To solve this, a single bit is forced to be one. This * slightly reduces the randomness but guarantees a good seed value. */ rndSeed |= 0x0080; /* * Two writes to RNDL will set the random seed. A write to RNDL copies current contents * of RNDL to RNDH before writing new the value to RNDL. */ RNDL = rndSeed & 0xFF; RNDL = rndSeed >> 8; } /* turn off the receiver, flush RX FIFO just in case something got in there */ RFST = ISRFOFF; /* flush the rx buffer */ MRFI_RADIO_FLUSH_RX_BUFFER(); /* take receiver out of infinite reception mode; set back to normal operation */ FRMCTRL0 = (FRMCTRL0 & ~RX_MODE_MASK) | RX_MODE_NORMAL; /* Initial radio state is OFF state */ mrfiRadioState = MRFI_RADIO_STATE_OFF; /* ------------------------------------------------------------------ * Configure Radio Registers * --------------------------- */ /* disable address filtering */ FRMFILT0 &= ~FRAME_FILTER_EN; /* reject beacon/ack/cmd frames and accept only data frames, * when filtering is enabled. */ FRMFILT1 &= ~(ACCEPT_BEACON | ACCEPT_ACK | ACCEPT_CMD); /* don't enable rx after tx is done. */ FRMCTRL1 &= ~RX_ENABLE_ON_TX; /* set FIFOP threshold to maximum */ FIFOPCTRL = 127; /* set default channel */ MRFI_SetLogicalChannel( 0 ); /* set default output power level */ MRFI_SetRFPwr(MRFI_NUM_POWER_SETTINGS - 1); /* enable general RF interrupts */ IEN2 |= RFIE; /* ------------------------------------------------------------------ * Final Initialization * ----------------------- */ /********************************************************************************** * Compute reply delay scalar * * The IEEE radio has a fixed data rate of 250 Kbps. Data rate inference * from radio regsiters is not necessary for this radio. * * The maximum delay needed depends on the MAX_APP_PAYLOAD parameter. Figure * out how many bits that will be when overhead is included. Bits/bits-per-second * is seconds to transmit (or receive) the maximum frame. We multiply this number * by 1000 to find the time in milliseconds. We then additionally multiply by * 10 so we can add 5 and divide by 10 later, thus rounding up to the number of * milliseconds. This last won't matter for slow transmissions but for faster ones * we want to err on the side of being conservative and making sure the radio is on * to receive the reply. The semaphore monitor will shut it down. The delay adds in * a platform fudge factor that includes processing time on peer plus lags in Rx and * processing time on receiver's side. Also includes round trip delays from CCA * retries. This portion is included in PLATFORM_FACTOR_CONSTANT defined in mrfi.h. * * ********************************************************************************** */ #define PHY_PREAMBLE_SYNC_BYTES 8 { uint32_t bits, dataRate = 250000; bits = ((uint32_t)((PHY_PREAMBLE_SYNC_BYTES + MRFI_MAX_FRAME_SIZE)*8))*10000; /* processing on the peer + the Tx/Rx time plus more */ sReplyDelayScalar = PLATFORM_FACTOR_CONSTANT + (((bits/dataRate)+5)/10); } /* * Random delay - This prevents devices on the same power source from repeated * transmit collisions on power up. */ Mrfi_RandomBackoffDelay(); /* enable global interrupts */ BSP_ENABLE_INTERRUPTS(); }
/************************************************************************************************** * @fn MRFI_Init * * @brief Initialize MRFI. * * @param none * * @return none ************************************************************************************************** */ void MRFI_Init(void) { /* ------------------------------------------------------------------ * Run-time integrity checks * --------------------------- */ /* verify the correct radio is installed */ MRFI_ASSERT( CHIPID == MRFI_RADIO_PARTNUM ); /* wrong radio */ MRFI_ASSERT( CHVER >= MRFI_RADIO_MIN_VERSION ); /* obsolete radio version */ /* ------------------------------------------------------------------ * Configure IO ports * --------------------------- */ #if defined(MRFI_PA_LNA_ENABLED) && defined(BSP_BOARD_SRF04EB) MRFI_BOARD_PA_LNA_CONFIG_PORTS(); MRFI_BOARD_PA_LNA_HGM(); #endif /* ------------------------------------------------------------------ * Configure clock to use XOSC * ----------------------------- */ SLEEP &= ~OSC_PD; /* turn on 16MHz RC and 32MHz XOSC */ while (!(SLEEP & XOSC_STB)); /* wait for 32MHz XOSC stable */ asm("NOP"); /* chip bug workaround */ { uint16_t i; /* Require 63us delay for all revs */ for (i=0; i<504; i++) { asm("NOP"); } } CLKCON = (0x00 | OSC_32KHZ); /* 32MHz XOSC */ while (CLKCON != (0x00 | OSC_32KHZ)); SLEEP |= OSC_PD; /* turn off 16MHz RC */ /* ------------------------------------------------------------------ * Variable Initialization * ------------------------- */ #ifdef MRFI_ASSERTS_ARE_ON PANIDL = 0xFF; PANIDH = 0xFF; #endif /* ------------------------------------------------------------------ * Initialize Random Seed Value * ------------------------------- */ /* turn on radio power, pend for the power-up delay */ RFPWR &= ~RREG_RADIO_PD; while((RFPWR & ADI_RADIO_PD)); /* * Set radio for infinite reception. Once radio reaches this state, * it will stay in receive mode regardless RF activity. */ MDMCTRL1L = MDMCTRL1L_RESET_VALUE | RX_MODE_INFINITE_RECEPTION; /* turn on the receiver */ RFST = ISRXON; /* * Wait for radio to reach infinite reception state. Once it does, * The least significant bit of ADTSTH should be pretty random. */ while (FSMSTATE != FSM_FFCTRL_STATE_RX_INF) /* put 16 random bits into the seed value */ { uint16_t rndSeed; uint8_t i; rndSeed = 0; for(i=0; i<16; i++) { /* use most random bit of analog to digital receive conversion to populate the random seed */ rndSeed = (rndSeed << 1) | (ADCTSTH & 0x01); } /* * The seed value must not be zero. If it is, the pseudo random sequence will be always be zero. * There is an extremely small chance this seed could randomly be zero (more likely some type of * hardware problem would cause this). To solve this, a single bit is forced to be one. This * slightly reduces the randomness but guarantees a good seed value. */ rndSeed |= 0x0080; /* * Two writes to RNDL will set the random seed. A write to RNDL copies current contents * of RNDL to RNDH before writing new the value to RNDL. */ RNDL = rndSeed & 0xFF; RNDL = rndSeed >> 8; } /* turn off the receiver, flush RX FIFO just in case something got in there */ RFST = ISRFOFF; /* flush the rx buffer */ MRFI_RADIO_FLUSH_RX_BUFFER(); /* take receiver out of infinite reception mode; set back to normal operation */ MDMCTRL1L = MDMCTRL1L_RESET_VALUE | RX_MODE_NORMAL_OPERATION; /* turn radio back off */ RFPWR |= RREG_RADIO_PD; /* Initial radio state is OFF state */ mrfiRadioState = MRFI_RADIO_STATE_OFF; /* ------------------------------------------------------------------ * Configure Radio Registers * --------------------------- */ /* tuning adjustments for optimal radio performance; details available in datasheet */ RXCTRL0H = 0x32; RXCTRL0L = 0xF5; /* disable address filtering */ MDMCTRL0H &= ~ADDR_DECODE; /* set FIFOP threshold to maximum */ IOCFG0 = 127; /* set default channel */ MRFI_SetLogicalChannel( 0 ); /* enable general RF interrupts */ IEN2 |= RFIE; /* ------------------------------------------------------------------ * Final Initialization * ----------------------- */ /********************************************************************************** * Compute reply delay scalar * * The IEEE radio has a fixed data rate of 250 Kbps. Data rate inference * from radio regsiters is not necessary for this radio. * * The maximum delay needed depends on the MAX_APP_PAYLOAD parameter. Figure * out how many bits that will be when overhead is included. Bits/bits-per-second * is seconds to transmit (or receive) the maximum frame. We multiply this number * by 1000 to find the time in milliseconds. We then additionally multiply by * 10 so we can add 5 and divide by 10 later, thus rounding up to the number of * milliseconds. This last won't matter for slow transmissions but for faster ones * we want to err on the side of being conservative and making sure the radio is on * to receive the reply. The semaphore monitor will shut it down. The delay adds in * a fudge factor that includes processing time on peer plus lags in Rx and processing * time on receiver's side. * * ********************************************************************************** */ #define PLATFORM_FACTOR_CONSTANT 2 #define PHY_PREAMBLE_SYNC_BYTES 8 { uint32_t bits, dataRate = 250000; bits = ((uint32_t)((PHY_PREAMBLE_SYNC_BYTES + MRFI_MAX_FRAME_SIZE)*8))*10000; /* processing on the peer + the Tx/Rx time plus more */ sReplyDelayScalar = PLATFORM_FACTOR_CONSTANT + (((bits/dataRate)+5)/10); } /* * Random delay - This prevents devices on the same power source from repeated * transmit collisions on power up. */ Mrfi_RandomBackoffDelay(); /* enable global interrupts */ BSP_ENABLE_INTERRUPTS(); }
// ************************************************************************************************* // @fn wbsl_config // @brief Configures the Radio Settings for WBSL // @param none // @return none // ************************************************************************************************* void wbsl_config(void) { if (!sInitWbslDone) { /* ------------------------------------------------------------------ * Initialization * ----------------- */ /* initialize GPIO pins */ WBSL_CONFIG_GDO0_PIN_AS_INPUT(); /* initialize SPI */ wbsl_SpiInit(); /* ------------------------------------------------------------------ * Radio power-up reset * ---------------------- */ WBSL_SPI_ASSERT(WBSL_SPI_CSN_IS_HIGH()); /* pulse CSn low then high */ WBSL_SPI_DRIVE_CSN_LOW(); wbsl_DelayUsec(10); WBSL_SPI_DRIVE_CSN_HIGH(); /* hold CSn high for at least 40 microseconds */ wbsl_DelayUsec(40); /* pull CSn low and wait for SO to go low */ WBSL_SPI_DRIVE_CSN_LOW(); while (WBSL_SPI_SO_IS_HIGH()); /* return CSn pin to its default high level */ WBSL_SPI_DRIVE_CSN_HIGH(); /* ------------------------------------------------------------------ * Run-time integrity checks * --------------------------- */ /* verify that SPI is working, PKTLEN is an arbitrary read/write register used for testing */ #ifdef WBSL_ASSERTS_ARE_ON #define TEST_VALUE 0xA5 wbsl_SpiWriteReg( PKTLEN, TEST_VALUE ); WBSL_SPI_ASSERT( mrfiSpiReadReg( PKTLEN ) == TEST_VALUE ); /* SPI is not responding */ #endif /* verify the correct radio is installed */ WBSL_SPI_ASSERT( wbsl_SpiReadReg( PARTNUM ) == WBSL_RADIO_PARTNUM ); /* incorrect radio specified */ WBSL_SPI_ASSERT( wbsl_SpiReadReg( VERSION ) >= WBSL_RADIO_MIN_VERSION ); /* obsolete radio specified */ /* ------------------------------------------------------------------ * Configure radio * ----------------- */ /* initialize radio registers */ { u8 i; for (i=0; i<(sizeof(wbslRadioCfg)/sizeof(wbslRadioCfg[0])); i++) { wbsl_SpiWriteReg(wbslRadioCfg[i][0], wbslRadioCfg[i][1]); } } /* ------------------------------------------------------------------ * Configure interrupts * ---------------------- */ /* * Configure and enable the SYNC signal interrupt. * * This interrupt is used to indicate receive. The SYNC signal goes * high when a receive OR a transmit begins. It goes high once the * sync word is received or transmitted and then goes low again once * the packet completes. */ WBSL_CONFIG_GDO0_AS_SYNC_SIGNAL(); WBSL_CONFIG_SYNC_PIN_FALLING_EDGE_INT(); WBSL_CLEAR_SYNC_PIN_INT_FLAG(); /* enable global interrupts */ BSP_ENABLE_INTERRUPTS(); } sInitWbslDone=1; }
/************************************************************************************************** * @fn MRFI_Init * * @brief Initialize MRFI. * * @param none * * @return none ************************************************************************************************** */ void MRFI_Init(void) { /* ------------------------------------------------------------------ * Initialization * ----------------- */ /* initialize radio state variables */ mrfiRxFilterEnabled = 0; mrfiRadioIsSleeping = 0; mrfiTxActive = 0; mrfiRxActive = 0; /* initialize GPIO pins */ MRFI_CONFIG_GDO0_PIN_AS_INPUT(); MRFI_CONFIG_GDO2_PIN_AS_INPUT(); /* initialize SPI */ mrfiSpiInit(); /* ------------------------------------------------------------------ * Radio power-up reset * ---------------------- */ MRFI_ASSERT(MRFI_SPI_CSN_IS_HIGH()); /* pulse CSn low then high */ MRFI_SPI_DRIVE_CSN_LOW(); MRFI_DELAY(10); MRFI_SPI_DRIVE_CSN_HIGH(); /* hold CSn high for at least 40 microseconds */ MRFI_DELAY(100); /* pull CSn low and wait for SO to go low */ MRFI_SPI_DRIVE_CSN_LOW(); while (MRFI_SPI_SO_IS_HIGH()); /* directly send strobe command - cannot use function as it affects CSn pin */ MRFI_SPI_WRITE_BYTE(MRFI_CC2500_SPI_STROBE_SRES); MRFI_SPI_WAIT_DONE(); /* wait for SO to go low again, reset is complete at that point */ while (MRFI_SPI_SO_IS_HIGH()); /* return CSn pin to its default high level */ MRFI_SPI_DRIVE_CSN_HIGH(); /* ------------------------------------------------------------------ * Run-time integrity checks * --------------------------- */ /* verify that SPI is working */ #ifdef MRFI_ASSERTS_ARE_ON #define TEST_VALUE 0xA5 mrfiSpiWriteReg( MRFI_CC2500_SPI_REG_PKTLEN, TEST_VALUE ); MRFI_ASSERT( mrfiSpiReadReg( MRFI_CC2500_SPI_REG_PKTLEN ) == TEST_VALUE ); /* SPI is not responding */ #endif /* verify the correct radio is installed */ MRFI_ASSERT( mrfiSpiReadReg( MRFI_CC2500_SPI_REG_PARTNUM ) == MRFI_RADIO_PARTNUM); /* incorrect radio specified */ MRFI_ASSERT( mrfiSpiReadReg( MRFI_CC2500_SPI_REG_VERSION ) >= MRFI_RADIO_MIN_VERSION); /* obsolete radio specified */ /* ------------------------------------------------------------------ * Configure radio * ----------------- */ /* initialize radio registers */ { uint8_t i; for (i=0; i<(sizeof(mrfiRadioCfg)/sizeof(mrfiRadioCfg[0])); i++) { mrfiSpiWriteReg(mrfiRadioCfg[i][0], mrfiRadioCfg[i][1]); } } /* send strobe to turn on receiver */ mrfiSpiCmdStrobe(MRFI_CC2500_SPI_STROBE_SRX); /* ------------------------------------------------------------------ * Configure interrupts * ---------------------- */ /* * Configure and enable the SYNC signal interrupt. * * This interrupt is used to indicate receive. The SYNC signal goes * high when a receive OR a transmit begins. It goes high once the * sync word is received or transmitted and then goes low again once * the packet completes. */ MRFI_CONFIG_SYNC_PIN_FALLING_EDGE_INT(); MRFI_CLEAR_SYNC_PIN_INT_FLAG(); MRFI_ENABLE_SYNC_PIN_INT(); /* configure PA_PD signal interrupt */ MRFI_CONFIG_PAPD_FALLING_EDGE_INT(); /* enable global interrupts */ BSP_ENABLE_INTERRUPTS(); }