static void PIOS_EXTI_15_10_irq_handler (void) { #if defined(PIOS_INCLUDE_CHIBIOS) CH_IRQ_PROLOGUE(); #endif /* defined(PIOS_INCLUDE_CHIBIOS) */ #if defined(PIOS_INCLUDE_FREERTOS) portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; #else bool xHigherPriorityTaskWoken; #endif PIOS_EXTI_HANDLE_LINE(10, xHigherPriorityTaskWoken); PIOS_EXTI_HANDLE_LINE(11, xHigherPriorityTaskWoken); PIOS_EXTI_HANDLE_LINE(12, xHigherPriorityTaskWoken); PIOS_EXTI_HANDLE_LINE(13, xHigherPriorityTaskWoken); PIOS_EXTI_HANDLE_LINE(14, xHigherPriorityTaskWoken); PIOS_EXTI_HANDLE_LINE(15, xHigherPriorityTaskWoken); #if defined(PIOS_INCLUDE_FREERTOS) portEND_SWITCHING_ISR(xHigherPriorityTaskWoken); #else (void)xHigherPriorityTaskWoken; #endif #if defined(PIOS_INCLUDE_CHIBIOS) CH_IRQ_EPILOGUE(); #endif /* defined(PIOS_INCLUDE_CHIBIOS) */ }
void EXTI15_10_IRQHandler(void) { CH_IRQ_PROLOGUE(); chSysLockFromIsr(); Adc.IIrqExtiHandler(); chSysUnlockFromIsr(); CH_IRQ_EPILOGUE(); }
/** * @brief Interrupt simulation. */ void ChkIntSources(void) { LARGE_INTEGER n; #if HAL_USE_SERIAL if (sd_lld_interrupt_pending()) { dbg_check_lock(); if (chSchIsPreemptionRequired()) chSchDoReschedule(); dbg_check_unlock(); return; } #endif /* Interrupt Timer simulation (10ms interval).*/ QueryPerformanceCounter(&n); if (n.QuadPart > nextcnt.QuadPart) { nextcnt.QuadPart += slice.QuadPart; CH_IRQ_PROLOGUE(); chSysLockFromIsr(); chSysTimerHandlerI(); chSysUnlockFromIsr(); CH_IRQ_EPILOGUE(); dbg_check_lock(); if (chSchIsPreemptionRequired()) chSchDoReschedule(); dbg_check_unlock(); } else { /* Avoid CPU spinning */ Sleep(1); } }
/** DMA 1 Stream 1 Interrupt Service Routine. */ void dma1_stream1_isr(void) { CH_IRQ_PROLOGUE(); chSysLockFromIsr(); usart_rx_dma_isr(&uartb_state.rx); chSysUnlockFromIsr(); CH_IRQ_EPILOGUE(); }
/** DMA 2 Stream 7 Interrupt Service Routine. */ void dma2_stream7_isr(void) { CH_IRQ_PROLOGUE(); chSysLockFromIsr(); usart_tx_dma_isr(&uarta_state.tx); chSysUnlockFromIsr(); CH_IRQ_EPILOGUE(); }
/* * Non-vectored IRQs handler, the default action can be overridden by * redefining the @p LPC214x_NON_VECTORED_IRQ_HOOK() hook macro. */ static CH_IRQ_HANDLER(irq_handler) { CH_IRQ_PROLOGUE(); LPC214x_NON_VECTORED_IRQ_HOOK(); VICVectAddr = 0; CH_IRQ_EPILOGUE(); }
void TIM2_IRQHandler(void) { CH_IRQ_PROLOGUE(); chSysLockFromIsr(); if(TIM2->SR & TIM_SR_UIF) { TIM2->SR &= ~TIM_SR_UIF; Adc.IIrqSmpHandler(); } chSysUnlockFromIsr(); CH_IRQ_EPILOGUE(); }
void TIM5_IRQHandler(void) { CH_IRQ_PROLOGUE(); chSysLockFromIsr(); if(TIM5->SR & TIM_SR_UIF) { TIM5->SR &= ~TIM_SR_UIF; TIM5->CCER; Adc.IIrqHandler(); } chSysUnlockFromIsr(); CH_IRQ_EPILOGUE(); }
/** DMA 2 Stream 3 Interrupt Service Routine. (SPI1_TX) */ void dma2_stream3_isr(void) { CH_IRQ_PROLOGUE(); chSysLockFromIsr(); if (dma_get_interrupt_flag(DMA2, 3, DMA_TEIF | DMA_DMEIF)) screaming_death("DMA SPI1_TX error interrupt"); chSysUnlockFromIsr(); CH_IRQ_EPILOGUE(); }
/* * Timer 0 IRQ handling here. */ static CH_IRQ_HANDLER(T0IrqHandler) { CH_IRQ_PROLOGUE(); T0IR = 1; /* Clear interrupt on match MR0. */ chSysLockFromIsr(); chSysTimerHandlerI(); chSysUnlockFromIsr(); VICVectAddr = 0; CH_IRQ_EPILOGUE(); }
static void PIOS_USART_6_irq_handler (void) { #if defined(PIOS_INCLUDE_CHIBIOS) CH_IRQ_PROLOGUE(); #endif /* defined(PIOS_INCLUDE_CHIBIOS) */ PIOS_USART_generic_irq_handler (PIOS_USART_6_id); #if defined(PIOS_INCLUDE_CHIBIOS) CH_IRQ_EPILOGUE(); #endif /* defined(PIOS_INCLUDE_CHIBIOS) */ }
void CAN2_TX_IRQHandler(void) { #if defined(PIOS_INCLUDE_CHIBIOS) CH_IRQ_PROLOGUE(); #endif /* defined(PIOS_INCLUDE_CHIBIOS) */ PIOS_CAN_TxGeneric(); #if defined(PIOS_INCLUDE_CHIBIOS) CH_IRQ_EPILOGUE(); #endif /* defined(PIOS_INCLUDE_CHIBIOS) */ }
bool_t sd_lld_interrupt_pending(void) { bool_t b; CH_IRQ_PROLOGUE(); b = connint(&SD1) || connint(&SD2) || inint(&SD1) || inint(&SD2) || outint(&SD1) || outint(&SD2); CH_IRQ_EPILOGUE(); return b; }
/* * SYS IRQ handling here. */ static CH_IRQ_HANDLER(SYSIrqHandler) { CH_IRQ_PROLOGUE(); if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { (void) AT91C_BASE_PITC->PITC_PIVR; chSysLockFromIsr(); chSysTimerHandlerI(); chSysUnlockFromIsr(); } AT91C_BASE_AIC->AIC_EOICR = 0; CH_IRQ_EPILOGUE(); }
bool sd_lld_interrupt_pending(void) { bool b = false; CH_IRQ_PROLOGUE(); #if USE_WIN32_SERIAL1 b |= connint(&SD1) || inint(&SD1) || outint(&SD1); #endif #if USE_WIN32_SERIAL2 b |= connint(&SD2) || inint(&SD2) || outint(&SD2); #endif CH_IRQ_EPILOGUE(); return b; }
/** DMA 2 Stream 0 Interrupt Service Routine. (SPI1_RX) */ void dma2_stream0_isr(void) { CH_IRQ_PROLOGUE(); chSysLockFromIsr(); if (dma_get_interrupt_flag(DMA2, 0, DMA_TEIF | DMA_DMEIF)) screaming_death("DMA SPI1_RX error interrupt"); /* Disable both receive and transmit streams */ dma_clear_interrupt_flags(DMA2, 3, DMA_TCIF | DMA_HTIF); dma_clear_interrupt_flags(DMA2, 0, DMA_TCIF | DMA_HTIF); /* Signal the semaphore to wake up blocking spi1_xfer_dma */ chBSemSignalI(&spi_dma_sem); chSysUnlockFromIsr(); CH_IRQ_EPILOGUE(); }
/* * SYS IRQ handling here. */ static CH_IRQ_HANDLER(SYSIrqHandler) { CH_IRQ_PROLOGUE(); if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { (void) AT91C_BASE_PITC->PITC_PIVR; chSysLockFromIsr(); chSysTimerHandlerI(); chSysUnlockFromIsr(); } #if USE_SAM7_DBGU_UART if (AT91C_BASE_DBGU->DBGU_CSR & (AT91C_US_RXRDY | AT91C_US_TXRDY | AT91C_US_PARE | AT91C_US_FRAME | AT91C_US_OVRE | AT91C_US_RXBRK)) { sd_lld_serve_interrupt(&SDDBG); } #endif AT91C_BASE_AIC->AIC_EOICR = 0; CH_IRQ_EPILOGUE(); }
/******************************************************************************* * Function Name : USB_Istr * Description : STR events interrupt service routine * Input : * Output : * Return : *******************************************************************************/ void USB_LP_CAN1_RX0_IRQHandler(void) //USB_Istr(void) { #if defined(PIOS_INCLUDE_CHIBIOS) CH_IRQ_PROLOGUE(); #endif /* defined(PIOS_INCLUDE_CHIBIOS) */ wIstr = _GetISTR(); #if (IMR_MSK & ISTR_CTR) if (wIstr & ISTR_CTR & wInterrupt_Mask) { /* servicing of the endpoint correct transfer interrupt */ /* clear of the CTR flag into the sub */ CTR_LP(); #ifdef CTR_CALLBACK CTR_Callback(); #endif } #endif /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/ #if (IMR_MSK & ISTR_RESET) if (wIstr & ISTR_RESET & wInterrupt_Mask) { _SetISTR((uint16_t) CLR_RESET); Device_Property.Reset(); #ifdef RESET_CALLBACK RESET_Callback(); #endif } #endif /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/ #if (IMR_MSK & ISTR_DOVR) if (wIstr & ISTR_DOVR & wInterrupt_Mask) { _SetISTR((uint16_t) CLR_DOVR); #ifdef DOVR_CALLBACK DOVR_Callback(); #endif } #endif /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/ #if (IMR_MSK & ISTR_ERR) if (wIstr & ISTR_ERR & wInterrupt_Mask) { _SetISTR((uint16_t) CLR_ERR); #ifdef ERR_CALLBACK ERR_Callback(); #endif } #endif /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/ #if (IMR_MSK & ISTR_WKUP) if (wIstr & ISTR_WKUP & wInterrupt_Mask) { _SetISTR((uint16_t) CLR_WKUP); Resume(RESUME_EXTERNAL); #ifdef WKUP_CALLBACK WKUP_Callback(); #endif } #endif /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/ #if (IMR_MSK & ISTR_SUSP) if (wIstr & ISTR_SUSP & wInterrupt_Mask) { /* check if SUSPEND is possible */ if (fSuspendEnabled) { Suspend(); } else { /* if not possible then resume after xx ms */ Resume(RESUME_LATER); } /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ _SetISTR((uint16_t) CLR_SUSP); #ifdef SUSP_CALLBACK SUSP_Callback(); #endif } #endif /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/ #if (IMR_MSK & ISTR_SOF) if (wIstr & ISTR_SOF & wInterrupt_Mask) { _SetISTR((uint16_t) CLR_SOF); bIntPackSOF++; #ifdef SOF_CALLBACK SOF_Callback(); #endif } #endif /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/ #if (IMR_MSK & ISTR_ESOF) if (wIstr & ISTR_ESOF & wInterrupt_Mask) { _SetISTR((uint16_t) CLR_ESOF); /* resume handling timing is made with ESOFs */ Resume(RESUME_ESOF); /* request without change of the machine state */ #ifdef ESOF_CALLBACK ESOF_Callback(); #endif } #endif #if defined(PIOS_INCLUDE_CHIBIOS) CH_IRQ_EPILOGUE(); #endif /* defined(PIOS_INCLUDE_CHIBIOS) */ } /* USB_Istr */