// --------------------------------------------------------------------------
void adcInit(const UINT8 ui8_reference, const UINT8 ui8_prescaler)
{
ADC_InitTypeDef adc;
// suppress compiler complaints
(void)ui8_reference;
// configure ADC clock (must not exceed 14MHz)
RCC_ADCCLKConfig(prescaler_reg[ui8_prescaler]);
RCC_APB2PeriphClockCmd(ADC_RCC, ENABLE);
// reset current settings
ADC_DeInit(ADC_PERIPH);
ADC_StructInit(&adc);
adc.ADC_Mode = ADC_Mode_Independent;
adc.ADC_ScanConvMode = DISABLE;
adc.ADC_ContinuousConvMode = DISABLE;
adc.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
adc.ADC_DataAlign = ADC_DataAlign_Right;
adc.ADC_NbrOfChannel = 1;
ADC_Init(ADC_PERIPH, &adc);
ADC_Cmd(ADC_PERIPH, ENABLE);
// perform calibration, not needed but it don't hurt
ADC_ResetCalibration(ADC_PERIPH);
WAIT_FOR(ADC_GetResetCalibrationStatus(ADC_PERIPH));
ADC_StartCalibration(ADC_PERIPH);
WAIT_FOR(ADC_GetCalibrationStatus(ADC_PERIPH));
}
void S12Iic_Start(S12Iic_ConfigType const * const Cfg)
{
if (!S12_IIC_ENABLED()) {
return;
}
WAIT_FOR((S12_REG8(Cfg, IBSR) & IBB) != IBB);
S12_REG8(Cfg, IBCR) |= (IBEN | MS_SL | TX_RX);
WAIT_FOR((S12_REG8(Cfg, IBSR) & IBB) == IBB);
}
static int
cuda_init_via()
{
int x;
via[DIRB] = (via[DIRB] | TACK | TIP) & ~TREQ; /* TACK & TIP out */
via[B] |= TACK | TIP; /* negate them */
via[ACR] = (via[ACR] & ~SR_CTRL) | SR_EXT; /* SR data in */
eieio();
x = via[SR];
eieio(); /* clear any left-over data */
#ifndef CONFIG_MAC
via[IER] = 0x7f;
eieio(); /* disable interrupts from VIA */
#endif
eieio();
/* delay 4ms and then clear any pending interrupt */
mdelay(4);
x = via[SR];
eieio();
/* sync with the CUDA - assert TACK without TIP */
via[B] &= ~TACK;
eieio();
/* wait for the CUDA to assert TREQ in response */
WAIT_FOR((via[B] & TREQ) == 0, "CUDA response to sync");
/* wait for the interrupt and then clear it */
WAIT_FOR(via[IFR] & SR_INT, "CUDA response to sync (2)");
x = via[SR];
eieio();
/* finish the sync by negating TACK */
via[B] |= TACK;
eieio();
/* wait for the CUDA to negate TREQ and the corresponding interrupt */
WAIT_FOR(via[B] & TREQ, "CUDA response to sync (3)");
WAIT_FOR(via[IFR] & SR_INT, "CUDA response to sync (4)");
x = via[SR];
eieio();
via[B] |= TIP;
eieio(); /* should be unnecessary */
return 0;
}
// --------------------------------------------------------------------------
void rs4xxSendByte(usart_cfg_st *usart, const BYTE c_byte)
{
RS4XX_TX_ENA();
usartSendByte(usart, c_byte);
WAIT_FOR(USART_GetFlagStatus((USART_TypeDef*)usart->usart_if, USART_FLAG_TC) == RESET);
RS4XX_TX_DIS();
}
void S12Sci_Put(uint8 Controller, uint8 ch)
{
VAR(uint16, AUTOMATIC) Base = S12Sci_ControllerMapping[Controller];
WAIT_FOR(((S12SCI_REG8(Base, SCISR1)) & TDRE) == TDRE);
S12SCI_REG8(Base, SCIDRL) = ch;
}
void S12Sci_Get(uint8 Controller, uint8 * ch)
{
VAR(uint16, AUTOMATIC) Base = S12Sci_ControllerMapping[Controller];
uint8 error;
WAIT_FOR(((S12SCI_REG8(Base, SCISR1)) & RDRF) == RDRF);
error = S12SCI_REG8(Base, SCISR1) & (OR | NF | FE | PF);
*ch = S12SCI_REG8(Base, SCIDRL);
}
static int
cuda_init_via(void)
{
out_8(&via[DIRB], (in_8(&via[DIRB]) | TACK | TIP) & ~TREQ); /* TACK & TIP out */
out_8(&via[B], in_8(&via[B]) | TACK | TIP); /* negate them */
out_8(&via[ACR] ,(in_8(&via[ACR]) & ~SR_CTRL) | SR_EXT); /* SR data in */
(void)in_8(&via[SR]); /* clear any left-over data */
#ifdef CONFIG_PPC
out_8(&via[IER], 0x7f); /* disable interrupts from VIA */
(void)in_8(&via[IER]);
#else
out_8(&via[IER], SR_INT); /* disable SR interrupt from VIA */
#endif
/* delay 4ms and then clear any pending interrupt */
mdelay(4);
(void)in_8(&via[SR]);
out_8(&via[IFR], SR_INT);
/* sync with the CUDA - assert TACK without TIP */
out_8(&via[B], in_8(&via[B]) & ~TACK);
/* wait for the CUDA to assert TREQ in response */
WAIT_FOR((in_8(&via[B]) & TREQ) == 0, "CUDA response to sync");
/* wait for the interrupt and then clear it */
WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (2)");
(void)in_8(&via[SR]);
out_8(&via[IFR], SR_INT);
/* finish the sync by negating TACK */
out_8(&via[B], in_8(&via[B]) | TACK);
/* wait for the CUDA to negate TREQ and the corresponding interrupt */
WAIT_FOR(in_8(&via[B]) & TREQ, "CUDA response to sync (3)");
WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (4)");
(void)in_8(&via[SR]);
out_8(&via[IFR], SR_INT);
out_8(&via[B], in_8(&via[B]) | TIP); /* should be unnecessary */
return 0;
}
static int
cuda_init_via(void)
{
out_8(&via[DIRB], (in_8(&via[DIRB]) | TACK | TIP) & ~TREQ);
out_8(&via[B], in_8(&via[B]) | TACK | TIP);
out_8(&via[ACR] ,(in_8(&via[ACR]) & ~SR_CTRL) | SR_EXT);
(void)in_8(&via[SR]);
#ifdef CONFIG_PPC
out_8(&via[IER], 0x7f);
(void)in_8(&via[IER]);
#else
out_8(&via[IER], SR_INT);
#endif
mdelay(4);
(void)in_8(&via[SR]);
out_8(&via[IFR], SR_INT);
out_8(&via[B], in_8(&via[B]) & ~TACK);
WAIT_FOR((in_8(&via[B]) & TREQ) == 0, "CUDA response to sync");
WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (2)");
(void)in_8(&via[SR]);
out_8(&via[IFR], SR_INT);
out_8(&via[B], in_8(&via[B]) | TACK);
WAIT_FOR(in_8(&via[B]) & TREQ, "CUDA response to sync (3)");
WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (4)");
(void)in_8(&via[SR]);
out_8(&via[IFR], SR_INT);
out_8(&via[B], in_8(&via[B]) | TIP);
return 0;
}
void flash_init(Qspi &qspi)
{
uint8_t status[QSPI_STATUS_REG_SIZE];
qspi_status_t ret;
qspi.cmd.build(QSPI_CMD_RDSR);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, status, QSPI_STATUS_REG_SIZE);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
qspi.cmd.build(QSPI_CMD_RSTEN);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WRSR_MAX_TIME, qspi);
qspi.cmd.build(QSPI_CMD_RST);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WAIT_MAX_TIME, qspi);
}
/** May read only once every 2 seconds or so. This is not enforced. */
uint8_t DHT::read(void) {
uint8_t data[5] = {0}; // read buffer
uint8_t data_i = 0, data_b = 0;
digitalWrite(_pin, LOW); // externally pulled up: don't use internal pullup
// now pull it low for ~20 milliseconds
pinMode(_pin, OUTPUT);
delay(20);
pinMode(_pin, INPUT);
delayMicroseconds(40);
// sensor will respond by pulling low for 80us and high for 80us
WAIT_FOR(HIGH, 90, 1);
WAIT_FOR(LOW, 90, 2);
for(int i = 0; i < 40; ++i){
uint8_t* byte = &data[i/8];
*byte <<= 1;
// then each bit is 50us of low, and then either 25 or 70 us of high (0/1)
WAIT_FOR(HIGH, 60, 3);
uint8_t elapsed = WAIT_FOR(LOW, 90, 4);
if(elapsed > 40){
*byte |= 0x1;
}
}
// check we read 40 bits and that the checksum matches
if (data[4] == ((data[0] + data[1] + data[2] + data[3]) & 0xFF)) {
humidity = (data[0] << 8) | data[1];
temperature = (data[2] << 8) | data[3];
return 0;
}
else{
return 5;
}
}
boolean S12Iic_Write(S12Iic_ConfigType const * const Cfg, uint8 b)
{
boolean ack;
if (!S12_IIC_ENABLED()) {
return FALSE;
}
S12_REG8(Cfg, IBCR) |= TX_RX;
S12_REG8(Cfg, IBDR) = b;
WAIT_FOR((S12_REG8(Cfg, IBSR) & IBIF) == IBIF);
ack = ((S12_REG8(Cfg, IBSR) & RXAK) != RXAK);
S12_REG8(Cfg, IBSR) = IBIF;
return ack;
}
qspi_status_t write_disable(Qspi &qspi)
{
uint8_t reg[QSPI_STATUS_REG_SIZE];
qspi.cmd.build(QSPI_CMD_WRDI);
if (qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0) != QSPI_STATUS_OK) {
return QSPI_STATUS_ERROR;
}
WAIT_FOR(WRSR_MAX_TIME, qspi);
memset(reg, 0, QSPI_STATUS_REG_SIZE);
if (read_register(STATUS_REG, reg, QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) {
return QSPI_STATUS_ERROR;
}
return ((reg[0] & STATUS_BIT_WEL) == 0 ? QSPI_STATUS_OK : QSPI_STATUS_ERROR);
}
void S12Iic_Read(S12Iic_ConfigType const * const Cfg, uint8 * b, boolean ack)
{
if (!S12_IIC_ENABLED()) {
return;
}
if (ack) {
S12_REG8(Cfg, IBCR) &= ~TXAK;
} else {
S12_REG8(Cfg, IBCR) |= TXAK;
}
S12_REG8(Cfg, IBCR) &= ~TX_RX;
*b = S12_REG8(Cfg, IBDR); /* Dummy Read. */
WAIT_FOR((S12_REG8(Cfg, IBSR) & TCF) == TCF); /* WAIT_FOR((S12_REG8(Cfg,IBSR) & IBIF)==IBIF); */
S12_REG8(Cfg, IBSR) = IBIF;
*b = S12_REG8(Cfg, IBDR);
}
BOOST_FIXTURE_TEST_CASE(subscribe, NotifFixture) {
struct stat buffer;
WAIT_FOR(stat(SOCK_NAME.c_str(), &buffer) == 0, 500);
LOG(INFO) << "Connecting";
stream_protocol::socket s(io);
s.connect(stream_protocol::endpoint(SOCK_NAME));
StringBuffer r;
Writer<StringBuffer> writer(r);
writer.StartObject();
writer.Key("method");
writer.String("subscribe");
writer.Key("params");
writer.StartObject();
writer.Key("type");
writer.StartArray();
writer.String("virtual-ip");
writer.EndArray();
writer.EndObject();
writer.Key("id");
writer.String("1");
writer.EndObject();
std::string t("test");
uint32_t size = htonl(r.GetSize());
ba::write(s, ba::buffer(&size, 4));
ba::write(s, ba::buffer(r.GetString(), r.GetSize()));
Document rdoc;
readMessage(s, rdoc);
//StringBuffer output;
//{
// PrettyWriter<StringBuffer> owriter(output);
// rdoc.Accept(owriter);
// LOG(INFO) << std::endl << output.GetString();
//}
{
boost::unordered_set<std::string> uuids;
uuids.insert("4412dcd2-0cd0-4741-99d1-d8b3946e1fa9");
uuids.insert("1cc9483a-8d7a-48d5-9c23-862401691e01");
notif.dispatchVirtualIp(uuids,
opflex::modb::MAC("11:22:33:44:55:66"),
"1.2.3.4");
}
Document notif;
readMessage(s, notif);
BOOST_REQUIRE(notif.HasMember("method"));
BOOST_REQUIRE(notif["method"].IsString());
BOOST_CHECK_EQUAL("virtual-ip",
std::string(notif["method"].GetString()));
BOOST_REQUIRE(notif.HasMember("params"));
BOOST_REQUIRE(notif["params"].IsObject());
const rapidjson::Value& p = notif["params"];
BOOST_REQUIRE(p.HasMember("mac"));
BOOST_REQUIRE(p["mac"].IsString());
BOOST_CHECK_EQUAL("11:22:33:44:55:66",
std::string(p["mac"].GetString()));
BOOST_REQUIRE(p.HasMember("ip"));
BOOST_REQUIRE(p["ip"].IsString());
BOOST_CHECK_EQUAL("1.2.3.4",
std::string(p["ip"].GetString()));
BOOST_REQUIRE(p.HasMember("uuid"));
BOOST_REQUIRE(p["uuid"].IsArray());
std::set<std::string> us;
const rapidjson::Value& uuids = p["uuid"];
rapidjson::Value::ConstValueIterator it;
for (it = uuids.Begin(); it != uuids.End(); ++it) {
BOOST_REQUIRE(it->IsString());
us.insert(it->GetString());
}
BOOST_CHECK_EQUAL(2, us.size());
BOOST_CHECK(us.find("4412dcd2-0cd0-4741-99d1-d8b3946e1fa9") != us.end());
BOOST_CHECK(us.find("1cc9483a-8d7a-48d5-9c23-862401691e01") != us.end());
//output.Clear();
//{
// PrettyWriter<StringBuffer> owriter(output);
// notif.Accept(owriter);
// LOG(INFO) << std::endl << output.GetString();
//}
}
/*
* Get device state. Called with statlock and PHY lock held.
*/
static int
pmcs_get_dev_state(pmcs_hw_t *pwp, pmcs_phy_t *phyp, pmcs_xscsi_t *xp,
uint8_t *ds)
{
uint32_t htag, *ptr, msg[PMCS_MSG_SIZE];
int result;
struct pmcwork *pwrk;
pmcs_prt(pwp, PMCS_PRT_DEBUG3, phyp, xp, "%s: tgt(0x%p)", __func__,
(void *)xp);
if (xp != NULL) {
ASSERT(mutex_owned(&xp->statlock));
}
if (phyp == NULL) {
pmcs_prt(pwp, PMCS_PRT_DEBUG_DEV_STATE, NULL, xp,
"%s: PHY is NULL", __func__);
return (-1);
}
ASSERT(mutex_owned(&phyp->phy_lock));
pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, phyp);
if (pwrk == NULL) {
pmcs_prt(pwp, PMCS_PRT_ERR, phyp, xp, pmcs_nowrk, __func__);
return (-1);
}
pwrk->arg = msg;
pwrk->dtype = phyp->dtype;
if (phyp->valid_device_id == 0) {
pmcs_pwork(pwp, pwrk);
pmcs_prt(pwp, PMCS_PRT_DEBUG, phyp, xp,
"%s: Invalid DeviceID", __func__);
return (-1);
}
htag = pwrk->htag;
msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL,
PMCIN_GET_DEVICE_STATE));
msg[1] = LE_32(pwrk->htag);
msg[2] = LE_32(phyp->device_id);
CLEAN_MESSAGE(msg, 3);
mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]);
ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER);
if (ptr == NULL) {
mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]);
pmcs_pwork(pwp, pwrk);
pmcs_prt(pwp, PMCS_PRT_ERR, phyp, xp, pmcs_nomsg, __func__);
return (-1);
}
COPY_MESSAGE(ptr, msg, PMCS_MSG_SIZE);
pwrk->state = PMCS_WORK_STATE_ONCHIP;
INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER);
if (xp != NULL) {
mutex_exit(&xp->statlock);
}
pmcs_unlock_phy(phyp);
WAIT_FOR(pwrk, 1000, result);
pmcs_pwork(pwp, pwrk);
pmcs_lock_phy(phyp);
if (xp != NULL) {
mutex_enter(&xp->statlock);
}
if (result) {
pmcs_timed_out(pwp, htag, __func__);
pmcs_prt(pwp, PMCS_PRT_DEBUG, phyp, xp,
"%s: cmd timed out, returning", __func__);
return (-1);
}
if (LE_32(msg[2]) == 0) {
*ds = (uint8_t)(LE_32(msg[4]));
if (xp == NULL) {
pmcs_prt(pwp, PMCS_PRT_DEBUG_DEV_STATE, phyp, xp,
"%s: retrieved_ds=0x%x", __func__, *ds);
} else if (*ds != xp->dev_state) {
pmcs_prt(pwp, PMCS_PRT_DEBUG_DEV_STATE, phyp, xp,
"%s: retrieved_ds=0x%x, target_ds=0x%x", __func__,
*ds, xp->dev_state);
}
return (0);
} else {
pmcs_prt(pwp, PMCS_PRT_DEBUG_DEV_STATE, phyp, xp,
"%s: cmd failed Status(0x%x), returning ", __func__,
LE_32(msg[2]));
return (-1);
}
}
/*
* Set device state. Called with target's statlock and PHY lock held.
*/
static int
pmcs_set_dev_state(pmcs_hw_t *pwp, pmcs_phy_t *phyp, pmcs_xscsi_t *xp,
uint8_t ds)
{
uint32_t htag, *ptr, msg[PMCS_MSG_SIZE];
int result;
uint8_t pds, nds;
struct pmcwork *pwrk;
pmcs_prt(pwp, PMCS_PRT_DEBUG_DEV_STATE, phyp, xp,
"%s: ds: 0x%x tgt: 0x%p phy: 0x%p", __func__, ds, (void *)xp,
(void *)phyp);
if (phyp == NULL) {
pmcs_prt(pwp, PMCS_PRT_DEBUG_DEV_STATE, NULL, xp,
"%s: PHY is NULL", __func__);
return (-1);
}
pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, phyp);
if (pwrk == NULL) {
pmcs_prt(pwp, PMCS_PRT_ERR, phyp, xp, pmcs_nowrk, __func__);
return (-1);
}
if (phyp->valid_device_id == 0) {
pmcs_pwork(pwp, pwrk);
pmcs_prt(pwp, PMCS_PRT_DEBUG_DEV_STATE, phyp, xp,
"%s: Invalid DeviceID", __func__);
return (-1);
}
pwrk->arg = msg;
pwrk->dtype = phyp->dtype;
htag = pwrk->htag;
msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL,
PMCIN_SET_DEVICE_STATE));
msg[1] = LE_32(pwrk->htag);
msg[2] = LE_32(phyp->device_id);
msg[3] = LE_32(ds);
CLEAN_MESSAGE(msg, 4);
mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]);
ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER);
if (ptr == NULL) {
mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]);
pmcs_pwork(pwp, pwrk);
pmcs_prt(pwp, PMCS_PRT_ERR, phyp, xp, pmcs_nomsg, __func__);
return (-1);
}
COPY_MESSAGE(ptr, msg, PMCS_MSG_SIZE);
pwrk->state = PMCS_WORK_STATE_ONCHIP;
INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER);
if (xp != NULL) {
mutex_exit(&xp->statlock);
}
pmcs_unlock_phy(phyp);
WAIT_FOR(pwrk, 1000, result);
pmcs_pwork(pwp, pwrk);
pmcs_lock_phy(phyp);
if (xp != NULL) {
mutex_enter(&xp->statlock);
}
if (result) {
pmcs_timed_out(pwp, htag, __func__);
pmcs_prt(pwp, PMCS_PRT_DEBUG_DEV_STATE, phyp, xp,
"%s: cmd timed out, returning", __func__);
return (-1);
}
if (LE_32(msg[2]) == 0) {
pds = (uint8_t)(LE_32(msg[4]) >> 4);
nds = (uint8_t)(LE_32(msg[4]) & 0x0000000f);
pmcs_prt(pwp, PMCS_PRT_DEBUG_DEV_STATE, phyp, xp,
"%s: previous_ds=0x%x, new_ds=0x%x", __func__, pds, nds);
if (xp != NULL) {
xp->dev_state = nds;
}
return (0);
} else {
