static long long sse4a_test_extrqi (long long in) { __m128i v1; long long pad =0x0; LI v_out; v1 = _mm_set_epi64x (pad, in); v_out.vec = _mm_extracti_si64 (v1, (unsigned int) 0x10,(unsigned int) 0x08); return (v_out.i[0]); }
static void TEST (void) { union128i_q u; long long e; u.x = _mm_set_epi64x (4294967295133LL, 3844294967295133LL); e = test (u.x); if (e != u.a[0]) abort (); }
__m128i mul_check(void) { __m128i x; //x = _mm_set_epi64x(0x0f0e0d0c0b0a0908, 0x0706050403020100); x = _mm_set_epi64x(0x0000000000000000, 0x00000000000000f0); //x = _mm_set_epi64x(0x0f0e0d030b0a0908, 0x0706050403020100); x = M128(x); return x; }
uint seqRank ( uint * vector , byte searchedByte , uint position ){ register uint i , cont = 0; __m128i patt , window , returnValue ; byte * c1 , patt_code [16]; uint d = position > >4 , r = position & 0 xf ; for ( i =0; i <16; i ++) patt_code [i ]= searchedByte ; long long * pat_array = ( long long *) patt_code ; patt = _mm_set_epi64x ( pat_array [1] , pat_array [0]) ; long long * text_array = ( long long *) vector ; for ( i =0; i <d; i ++) { window = _mm_set_epi64x ( text_array [1] , text_array [0]) ; returnValue = _mm_cmpestrm ( patt , 16 , window , 16 , mode ) ; cont += _mm_popcnt_u32 ( _mm_extract_epi32 ( returnValue ,0) ); text_array += 2; } window = _mm_set_epi64x ( text_array [1] , text_array [0]) ; returnValue = _mm_cmpestrm ( patt , r , window , r , mode ); cont += _mm_popcnt_u32 ( _mm_extract_epi32 ( returnValue ,0) ) +r -16; return cont ; }
static inline void vtx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf *pkt, uint64_t flags) { uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA | ((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT) | ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT)); __m128i descriptor = _mm_set_epi64x(high_qw, pkt->buf_physaddr + pkt->data_off); _mm_store_si128((__m128i *)txdp, descriptor); }
static inline void inner_product_gint16_linear_1_sse2 (gint16 * o, const gint16 * a, const gint16 * b, gint len, const gint16 * icoeff, gint bstride) { gint i = 0; __m128i sum[2], t; __m128i f = _mm_set_epi64x (0, *((gint64 *) icoeff)); const gint16 *c[2] = { (gint16 *) ((gint8 *) b + 0 * bstride), (gint16 *) ((gint8 *) b + 1 * bstride) }; sum[0] = sum[1] = _mm_setzero_si128 (); f = _mm_unpacklo_epi16 (f, sum[0]); for (; i < len; i += 16) { t = _mm_loadu_si128 ((__m128i *) (a + i + 0)); sum[0] = _mm_add_epi32 (sum[0], _mm_madd_epi16 (t, _mm_load_si128 ((__m128i *) (c[0] + i + 0)))); sum[1] = _mm_add_epi32 (sum[1], _mm_madd_epi16 (t, _mm_load_si128 ((__m128i *) (c[1] + i + 0)))); t = _mm_loadu_si128 ((__m128i *) (a + i + 8)); sum[0] = _mm_add_epi32 (sum[0], _mm_madd_epi16 (t, _mm_load_si128 ((__m128i *) (c[0] + i + 8)))); sum[1] = _mm_add_epi32 (sum[1], _mm_madd_epi16 (t, _mm_load_si128 ((__m128i *) (c[1] + i + 8)))); } sum[0] = _mm_srai_epi32 (sum[0], PRECISION_S16); sum[1] = _mm_srai_epi32 (sum[1], PRECISION_S16); sum[0] = _mm_madd_epi16 (sum[0], _mm_shuffle_epi32 (f, _MM_SHUFFLE (0, 0, 0, 0))); sum[1] = _mm_madd_epi16 (sum[1], _mm_shuffle_epi32 (f, _MM_SHUFFLE (1, 1, 1, 1))); sum[0] = _mm_add_epi32 (sum[0], sum[1]); sum[0] = _mm_add_epi32 (sum[0], _mm_shuffle_epi32 (sum[0], _MM_SHUFFLE (2, 3, 2, 3))); sum[0] = _mm_add_epi32 (sum[0], _mm_shuffle_epi32 (sum[0], _MM_SHUFFLE (1, 1, 1, 1))); sum[0] = _mm_add_epi32 (sum[0], _mm_set1_epi32 (1 << (PRECISION_S16 - 1))); sum[0] = _mm_srai_epi32 (sum[0], PRECISION_S16); sum[0] = _mm_packs_epi32 (sum[0], sum[0]); *o = _mm_extract_epi16 (sum[0], 0); }
/* constant-time doubling in GF(2^128) */ static __m128i gf128_mul2(const __m128i x) { const __m128i REDPOLY = _mm_set_epi64x(0, 0x87); const __m128i ZERO = _mm_setzero_si128(); __m128i x2; __m128i mask = _mm_cmpgt_epi32(ZERO, x); mask = _mm_shuffle_epi32(mask, 0xff); x2 = _mm_slli_epi64(x, 1) | _mm_srli_epi64(_mm_slli_si128(x, 8), 63); return x2 ^ (REDPOLY & mask); }
static UCS_F_ALWAYS_INLINE void uct_rc_mlx5_ep_set_rdma_seg(struct mlx5_wqe_raddr_seg *raddr, uint64_t rdma_raddr, uct_rkey_t rdma_rkey) { #ifdef __SSE4_2__ *(__m128i*)raddr = _mm_shuffle_epi8( _mm_set_epi64x(rdma_rkey, rdma_raddr), _mm_set_epi8(0, 0, 0, 0, /* reserved */ 8, 9, 10, 11, /* rkey */ 0, 1, 2, 3, 4, 5, 6, 7 /* rdma_raddr */ )); #else raddr->raddr = htonll(rdma_raddr); raddr->rkey = htonl(rdma_rkey); #endif }
static void TEST (void) { union128i_w u, s; union128i_q c; short e[8] = {0}; int i; s.x = _mm_set_epi16 (1, -2, 3, 4, 5, 6, -0x7000, 0x9000); c.x = _mm_set_epi64x (12, 13); u.x = test (s.x, c.x); if (c.a[0] < 16) for (i = 0; i < 8; i++) e[i] = s.a[i] >> c.a[0]; if (check_union128i_w (u, e)) abort (); }
static void TEST (void) { union128i_d u, s; union128i_q c; int e[4] = {0}; int i; s.x = _mm_set_epi32 (2, -3, 0x7000, 0x9000); c.x = _mm_set_epi64x (12, 23); u.x = test (s.x, c.x); if (c.a[0] < 32) for (i = 0; i < 4; i++) e[i] = s.a[i] << c.a[0]; if (check_union128i_d (u, e)) abort (); }
test (unsigned long long *v) { union { __m128i x; unsigned long long i[2]; } u; unsigned int i; u.x = _mm_set_epi64x (v[1], v[0]); for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) if (v[i] != u.i[i]) { #ifdef DEBUG printf ("%i: 0x%llx != 0x%llx\n", i, v[i], u.i[i]); #endif abort (); } }
static void TEST (void) { union128i_d u, s; union128i_q c; int e[4] = {0}; int i; s.x = _mm_set_epi32 (1, -2, 3, 4); c.x = _mm_set_epi64x (16, 29); u.x = test (s.x, c.x); if (c.a[0] < 32) for (i = 0; i < 4; i++) e[i] = s.a[i] >> c.a[0]; if (check_union128i_d (u, e)) abort (); }
static void TEST (void) { union128i_q u, s; long long e[2] = {0}; unsigned long long tmp; int i; s.x = _mm_set_epi64x (-1, 0xf); u.x = test (s.x); if (N < 64) for (i = 0; i < 2; i++) { tmp = s.a[i]; e[i] = tmp >> N; } if (check_union128i_q (u, e)) abort (); }
/* The GCM counter. Counts on the last 32 bits, ignoring carry. */ static inline void _nc_count_16_be_4 (uint64_t *init, uint64_t *dst, size_t blocks) { #if defined (__nc_SSE__) __m128i ctr, c1 = _mm_set_epi32 (1, 0, 0, 0), mask = _mm_set_epi64x (0x0c0d0e0f0b0a0908, 0x0706050403020100); ctr = _mm_shuffle_epi8 (_mm_loadu_si128 ((__m128i *) init), mask); for (; blocks --; dst += 2) { _mm_storeu_si128 ((__m128i *) dst, _mm_shuffle_epi8 (ctr, mask)); ctr = _mm_add_epi32 (ctr, c1); } #else uint64_t qw1 = init[0]; uint32_t dw3 = ((uint32_t*) init)[2], dw4 = be32toh (((uint32_t*) init)[3]); for (; blocks --; dst += 2) { dst[0] = qw1; ((uint32_t*) dst)[2] = dw3; ((uint32_t*) dst)[3] = htobe32 (dw4 ++); } #endif }
/*inline*/ void AES_reduced_batch_intr(__m128i* batch, uint32_t batch_size) //Encrypts batch_size in parallel { //Round Key initialization __m128i roundkey[AES_ROUNDS + 1]; for (unsigned i = 0; i<AES_ROUNDS + 1; ++i) { roundkey[i] = _mm_set_epi64x(subkeys64[i][1], subkeys64[i][0]); } for (unsigned i = 0; i<batch_size; ++i) { batch[i] = _mm_xor_si128(batch[i], roundkey[0]); } for (unsigned j = 0; j<AES_ROUNDS; ++j) { for (unsigned i = 0; i<batch_size; ++i) { batch[i] = _mm_aesenc_si128(batch[i], roundkey[j + 1]); } } }
int main() { __m128i var = _mm_set_epi64x(-1588454185101182573, 437384867522774919); print128_num(var); }
void intel_sha1_step(uint32_t *digest, const char *data, uint32_t num_blks) { __m128i abcd, e0, e1; __m128i abcd_save, e_save; __m128i msg0, msg1, msg2, msg3; __m128i shuf_mask, e_mask; #if 0 e_mask = _mm_set_epi64x(0xFFFFFFFF00000000ull, 0x0000000000000000ull); #else (void)e_mask; e0 = _mm_set_epi64x(0, 0); #endif shuf_mask = _mm_set_epi64x(0x0001020304050607ull, 0x08090a0b0c0d0e0full); // Load initial hash values abcd = _mm_loadu_si128((__m128i*) digest); e0 = _mm_insert_epi32(e0, *(digest+4), 3); abcd = _mm_shuffle_epi32(abcd, 0x1B); #if 0 e0 = _mm_and_si128(e0, e_mask); #endif while (num_blks > 0) { // Save hash values for addition after rounds abcd_save = abcd; e_save = e0; // Rounds 0-3 msg0 = _mm_loadu_si128((const __m128i*) data); msg0 = _mm_shuffle_epi8(msg0, shuf_mask); e0 = _mm_add_epi32(e0, msg0); e1 = abcd; abcd = _mm_sha1rnds4_epu32(abcd, e0, 0); // Rounds 4-7 msg1 = _mm_loadu_si128((const __m128i*) (data+16)); msg1 = _mm_shuffle_epi8(msg1, shuf_mask); e1 = _mm_sha1nexte_epu32(e1, msg1); e0 = abcd; abcd = _mm_sha1rnds4_epu32(abcd, e1, 0); msg0 = _mm_sha1msg1_epu32(msg0, msg1); // Rounds 8-11 msg2 = _mm_loadu_si128((const __m128i*) (data+32)); msg2 = _mm_shuffle_epi8(msg2, shuf_mask); e0 = _mm_sha1nexte_epu32(e0, msg2); e1 = abcd; abcd = _mm_sha1rnds4_epu32(abcd, e0, 0); msg1 = _mm_sha1msg1_epu32(msg1, msg2); msg0 = _mm_xor_si128(msg0, msg2); // Rounds 12-15 msg3 = _mm_loadu_si128((const __m128i*) (data+48)); msg3 = _mm_shuffle_epi8(msg3, shuf_mask); e1 = _mm_sha1nexte_epu32(e1, msg3); e0 = abcd; msg0 = _mm_sha1msg2_epu32(msg0, msg3); abcd = _mm_sha1rnds4_epu32(abcd, e1, 0); msg2 = _mm_sha1msg1_epu32(msg2, msg3); msg1 = _mm_xor_si128(msg1, msg3); // Rounds 16-19 e0 = _mm_sha1nexte_epu32(e0, msg0); e1 = abcd; msg1 = _mm_sha1msg2_epu32(msg1, msg0); abcd = _mm_sha1rnds4_epu32(abcd, e0, 0); msg3 = _mm_sha1msg1_epu32(msg3, msg0); msg2 = _mm_xor_si128(msg2, msg0); // Rounds 20-23 e1 = _mm_sha1nexte_epu32(e1, msg1); e0 = abcd; msg2 = _mm_sha1msg2_epu32(msg2, msg1); abcd = _mm_sha1rnds4_epu32(abcd, e1, 1); msg0 = _mm_sha1msg1_epu32(msg0, msg1); msg3 = _mm_xor_si128(msg3, msg1); // Rounds 24-27 e0 = _mm_sha1nexte_epu32(e0, msg2); e1 = abcd; msg3 = _mm_sha1msg2_epu32(msg3, msg2); abcd = _mm_sha1rnds4_epu32(abcd, e0, 1); msg1 = _mm_sha1msg1_epu32(msg1, msg2); msg0 = _mm_xor_si128(msg0, msg2); // Rounds 28-31 e1 = _mm_sha1nexte_epu32(e1, msg3); e0 = abcd; msg0 = _mm_sha1msg2_epu32(msg0, msg3); abcd = _mm_sha1rnds4_epu32(abcd, e1, 1); msg2 = _mm_sha1msg1_epu32(msg2, msg3); msg1 = _mm_xor_si128(msg1, msg3); // Rounds 32-35 e0 = _mm_sha1nexte_epu32(e0, msg0); e1 = abcd; msg1 = _mm_sha1msg2_epu32(msg1, msg0); abcd = _mm_sha1rnds4_epu32(abcd, e0, 1); msg3 = _mm_sha1msg1_epu32(msg3, msg0); msg2 = _mm_xor_si128(msg2, msg0); // Rounds 36-39 e1 = _mm_sha1nexte_epu32(e1, msg1); e0 = abcd; msg2 = _mm_sha1msg2_epu32(msg2, msg1); abcd = _mm_sha1rnds4_epu32(abcd, e1, 1); msg0 = _mm_sha1msg1_epu32(msg0, msg1); msg3 = _mm_xor_si128(msg3, msg1); // Rounds 40-43 e0 = _mm_sha1nexte_epu32(e0, msg2); e1 = abcd; msg3 = _mm_sha1msg2_epu32(msg3, msg2); abcd = _mm_sha1rnds4_epu32(abcd, e0, 2); msg1 = _mm_sha1msg1_epu32(msg1, msg2); msg0 = _mm_xor_si128(msg0, msg2); // Rounds 44-47 e1 = _mm_sha1nexte_epu32(e1, msg3); e0 = abcd; msg0 = _mm_sha1msg2_epu32(msg0, msg3); abcd = _mm_sha1rnds4_epu32(abcd, e1, 2); msg2 = _mm_sha1msg1_epu32(msg2, msg3); msg1 = _mm_xor_si128(msg1, msg3); // Rounds 48-51 e0 = _mm_sha1nexte_epu32(e0, msg0); e1 = abcd; msg1 = _mm_sha1msg2_epu32(msg1, msg0); abcd = _mm_sha1rnds4_epu32(abcd, e0, 2); msg3 = _mm_sha1msg1_epu32(msg3, msg0); msg2 = _mm_xor_si128(msg2, msg0); // Rounds 52-55 e1 = _mm_sha1nexte_epu32(e1, msg1); e0 = abcd; msg2 = _mm_sha1msg2_epu32(msg2, msg1); abcd = _mm_sha1rnds4_epu32(abcd, e1, 2); msg0 = _mm_sha1msg1_epu32(msg0, msg1); msg3 = _mm_xor_si128(msg3, msg1); // Rounds 56-59 e0 = _mm_sha1nexte_epu32(e0, msg2); e1 = abcd; msg3 = _mm_sha1msg2_epu32(msg3, msg2); abcd = _mm_sha1rnds4_epu32(abcd, e0, 2); msg1 = _mm_sha1msg1_epu32(msg1, msg2); msg0 = _mm_xor_si128(msg0, msg2); // Rounds 60-63 e1 = _mm_sha1nexte_epu32(e1, msg3); e0 = abcd; msg0 = _mm_sha1msg2_epu32(msg0, msg3); abcd = _mm_sha1rnds4_epu32(abcd, e1, 3); msg2 = _mm_sha1msg1_epu32(msg2, msg3); msg1 = _mm_xor_si128(msg1, msg3); // Rounds 64-67 e0 = _mm_sha1nexte_epu32(e0, msg0); e1 = abcd; msg1 = _mm_sha1msg2_epu32(msg1, msg0); abcd = _mm_sha1rnds4_epu32(abcd, e0, 3); msg3 = _mm_sha1msg1_epu32(msg3, msg0); msg2 = _mm_xor_si128(msg2, msg0); // Rounds 68-71 e1 = _mm_sha1nexte_epu32(e1, msg1); e0 = abcd; msg2 = _mm_sha1msg2_epu32(msg2, msg1); abcd = _mm_sha1rnds4_epu32(abcd, e1, 3); msg3 = _mm_xor_si128(msg3, msg1); // Rounds 72-75 e0 = _mm_sha1nexte_epu32(e0, msg2); e1 = abcd; msg3 = _mm_sha1msg2_epu32(msg3, msg2); abcd = _mm_sha1rnds4_epu32(abcd, e0, 3); // Rounds 76-79 e1 = _mm_sha1nexte_epu32(e1, msg3); e0 = abcd; abcd = _mm_sha1rnds4_epu32(abcd, e1, 3); // Add current hash values with previously saved e0 = _mm_sha1nexte_epu32(e0, e_save); abcd = _mm_add_epi32(abcd, abcd_save); data += 64; num_blks--; } abcd = _mm_shuffle_epi32(abcd, 0x1B); _mm_store_si128((__m128i*) digest, abcd); *(digest+4) = _mm_extract_epi32(e0, 3); }
static inline void desc_to_olflags_v(struct i40e_rx_queue *rxq, __m128i descs[4], struct rte_mbuf **rx_pkts) { const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer); __m128i rearm0, rearm1, rearm2, rearm3; __m128i vlan0, vlan1, rss, l3_l4e; /* mask everything except RSS, flow director and VLAN flags * bit2 is for VLAN tag, bit11 for flow director indication * bit13:12 for RSS indication. */ const __m128i rss_vlan_msk = _mm_set_epi32( 0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804); const __m128i cksum_mask = _mm_set_epi32( PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD | PKT_RX_EIP_CKSUM_BAD, PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD | PKT_RX_EIP_CKSUM_BAD, PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD | PKT_RX_EIP_CKSUM_BAD, PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD | PKT_RX_EIP_CKSUM_BAD); /* map rss and vlan type to rss hash and vlan flag */ const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED, 0, 0, 0, 0); const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0, 0, 0, PKT_RX_FDIR, 0); const __m128i l3_l4e_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, /* shift right 1 bit to make sure it not exceed 255 */ (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1, (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD) >> 1, (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1, (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1, (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1, (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1, PKT_RX_IP_CKSUM_BAD >> 1, (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1); vlan0 = _mm_unpackhi_epi32(descs[0], descs[1]); vlan1 = _mm_unpackhi_epi32(descs[2], descs[3]); vlan0 = _mm_unpacklo_epi64(vlan0, vlan1); vlan1 = _mm_and_si128(vlan0, rss_vlan_msk); vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1); rss = _mm_srli_epi32(vlan1, 11); rss = _mm_shuffle_epi8(rss_flags, rss); l3_l4e = _mm_srli_epi32(vlan1, 22); l3_l4e = _mm_shuffle_epi8(l3_l4e_flags, l3_l4e); /* then we shift left 1 bit */ l3_l4e = _mm_slli_epi32(l3_l4e, 1); /* we need to mask out the reduntant bits */ l3_l4e = _mm_and_si128(l3_l4e, cksum_mask); vlan0 = _mm_or_si128(vlan0, rss); vlan0 = _mm_or_si128(vlan0, l3_l4e); /* * At this point, we have the 4 sets of flags in the low 16-bits * of each 32-bit value in vlan0. * We want to extract these, and merge them with the mbuf init data * so we can do a single 16-byte write to the mbuf to set the flags * and all the other initialization fields. Extracting the * appropriate flags means that we have to do a shift and blend for * each mbuf before we do the write. */ rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 8), 0x10); rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 4), 0x10); rearm2 = _mm_blend_epi16(mbuf_init, vlan0, 0x10); rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(vlan0, 4), 0x10); /* write the rearm data and the olflags in one write */ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) != offsetof(struct rte_mbuf, rearm_data) + 8); RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) != RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16)); _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0); _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1); _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2); _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3); }
static inline int blake512_compress( state * state, const u8 * datablock ) { __m128i row1l; __m128i row2l; __m128i row3l; __m128i row4l; u64 row1hl, row1hh; u64 row2hl, row2hh; u64 row3hl, row3hh; u64 row4hl, row4hh; const __m128i r16 = _mm_setr_epi8(2,3,4,5,6,7,0,1,10,11,12,13,14,15,8,9); const __m128i u8to64 = _mm_set_epi8(8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7); union { __m128i u128[8]; u64 u64[16]; } m; __m128i t0, t1, t2, t3, t4, t5, t6, t7; u64 u0, u1, u2, u3; __m128i b0; u64 b1l, b1h; m.u128[0] = _mm_loadu_si128((__m128i*)(datablock + 0)); m.u128[1] = _mm_loadu_si128((__m128i*)(datablock + 16)); m.u128[2] = _mm_loadu_si128((__m128i*)(datablock + 32)); m.u128[3] = _mm_loadu_si128((__m128i*)(datablock + 48)); m.u128[4] = _mm_loadu_si128((__m128i*)(datablock + 64)); m.u128[5] = _mm_loadu_si128((__m128i*)(datablock + 80)); m.u128[6] = _mm_loadu_si128((__m128i*)(datablock + 96)); m.u128[7] = _mm_loadu_si128((__m128i*)(datablock + 112)); m.u128[0] = BSWAP64(m.u128[0]); m.u128[1] = BSWAP64(m.u128[1]); m.u128[2] = BSWAP64(m.u128[2]); m.u128[3] = BSWAP64(m.u128[3]); m.u128[4] = BSWAP64(m.u128[4]); m.u128[5] = BSWAP64(m.u128[5]); m.u128[6] = BSWAP64(m.u128[6]); m.u128[7] = BSWAP64(m.u128[7]); row1l = _mm_load_si128((__m128i*)&state->h[0]); row1hl = state->h[2]; row1hh = state->h[3]; row2l = _mm_load_si128((__m128i*)&state->h[4]); row2hl = state->h[6]; row2hh = state->h[7]; row3l = _mm_set_epi64x(0x13198A2E03707344ULL, 0x243F6A8885A308D3ULL); row3hl = 0xA4093822299F31D0ULL; row3hh = 0x082EFA98EC4E6C89ULL; row4l = _mm_set_epi64x(0xBE5466CF34E90C6CULL, 0x452821E638D01377ULL); row4hl = 0xC0AC29B7C97C50DDULL; row4hh = 0x3F84D5B5B5470917ULL; if(!state->nullt) { row4l = _mm_xor_si128(row4l, _mm_set1_epi64x(state->t[0])); row4hl ^= state->t[1]; row4hh ^= state->t[1]; } ROUND( 0); ROUND( 1); ROUND( 2); ROUND( 3); ROUND( 4); ROUND( 5); ROUND( 6); ROUND( 7); ROUND( 8); ROUND( 9); ROUND(10); ROUND(11); ROUND(12); ROUND(13); ROUND(14); ROUND(15); row1l = _mm_xor_si128(row3l,row1l); row1hl ^= row3hl; row1hh ^= row3hh; _mm_store_si128((__m128i*)&state->h[0], _mm_xor_si128(row1l, _mm_load_si128((__m128i*)&state->h[0]))); state->h[2] ^= row1hl; state->h[3] ^= row1hh; row2l = _mm_xor_si128(row4l,row2l); row2hl ^= row4hl; row2hh ^= row4hh; _mm_store_si128((__m128i*)&state->h[4], _mm_xor_si128(row2l, _mm_load_si128((__m128i*)&state->h[4]))); state->h[6] ^= row2hl; state->h[7] ^= row2hh; return 0; }
fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq) { uintptr_t p; struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */ mb_def.nb_segs = 1; /* data_off will be ajusted after new mbuf allocated for 512-byte * alignment. */ mb_def.data_off = RTE_PKTMBUF_HEADROOM; mb_def.port = rxq->port_id; rte_mbuf_refcnt_set(&mb_def, 1); /* prevent compiler reordering: rearm_data covers previous fields */ rte_compiler_barrier(); p = (uintptr_t)&mb_def.rearm_data; rxq->mbuf_initializer = *(uint64_t *)p; return 0; } static inline void fm10k_rxq_rearm(struct fm10k_rx_queue *rxq) { int i; uint16_t rx_id; volatile union fm10k_rx_desc *rxdp; struct rte_mbuf **mb_alloc = &rxq->sw_ring[rxq->rxrearm_start]; struct rte_mbuf *mb0, *mb1; __m128i head_off = _mm_set_epi64x( RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1, RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1); __m128i dma_addr0, dma_addr1; /* Rx buffer need to be aligned with 512 byte */ const __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX - FM10K_RX_DATABUF_ALIGN + 1); rxdp = rxq->hw_ring + rxq->rxrearm_start; /* Pull 'n' more MBUFs into the software ring */ if (rte_mempool_get_bulk(rxq->mp, (void *)mb_alloc, RTE_FM10K_RXQ_REARM_THRESH) < 0) { dma_addr0 = _mm_setzero_si128(); /* Clean up all the HW/SW ring content */ for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i++) { mb_alloc[i] = &rxq->fake_mbuf; _mm_store_si128((__m128i *)&rxdp[i].q, dma_addr0); } rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed += RTE_FM10K_RXQ_REARM_THRESH; return; } /* Initialize the mbufs in vector, process 2 mbufs in one loop */ for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i += 2, mb_alloc += 2) { __m128i vaddr0, vaddr1; uintptr_t p0, p1; mb0 = mb_alloc[0]; mb1 = mb_alloc[1]; /* Flush mbuf with pkt template. * Data to be rearmed is 6 bytes long. * Though, RX will overwrite ol_flags that are coming next * anyway. So overwrite whole 8 bytes with one load: * 6 bytes of rearm_data plus first 2 bytes of ol_flags. */ p0 = (uintptr_t)&mb0->rearm_data; *(uint64_t *)p0 = rxq->mbuf_initializer; p1 = (uintptr_t)&mb1->rearm_data; *(uint64_t *)p1 = rxq->mbuf_initializer; /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */ vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr); vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr); /* convert pa to dma_addr hdr/data */ dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0); dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1); /* add headroom to pa values */ dma_addr0 = _mm_add_epi64(dma_addr0, head_off); dma_addr1 = _mm_add_epi64(dma_addr1, head_off); /* Do 512 byte alignment to satisfy HW requirement, in the * meanwhile, set Header Buffer Address to zero. */ dma_addr0 = _mm_and_si128(dma_addr0, hba_msk); dma_addr1 = _mm_and_si128(dma_addr1, hba_msk); /* flush desc with pa dma_addr */ _mm_store_si128((__m128i *)&rxdp++->q, dma_addr0); _mm_store_si128((__m128i *)&rxdp++->q, dma_addr1); /* enforce 512B alignment on default Rx virtual addresses */ mb0->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb0->buf_addr + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN) - (char *)mb0->buf_addr); mb1->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb1->buf_addr + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN) - (char *)mb1->buf_addr); } rxq->rxrearm_start += RTE_FM10K_RXQ_REARM_THRESH; if (rxq->rxrearm_start >= rxq->nb_desc) rxq->rxrearm_start = 0; rxq->rxrearm_nb -= RTE_FM10K_RXQ_REARM_THRESH; rx_id = (uint16_t)((rxq->rxrearm_start == 0) ? (rxq->nb_desc - 1) : (rxq->rxrearm_start - 1)); /* Update the tail pointer on the NIC */ FM10K_PCI_REG_WRITE(rxq->tail_ptr, rx_id); }
__m128i long2vector(long long __i) { return _mm_set_epi64x (0, __i); }
int32_t end_query = 0; int32_t end_ref = 0; int64_t score = NEG_INF; int64_t matches = NEG_INF; int64_t similar = NEG_INF; int64_t length = NEG_INF; __m128i vNegInf = _mm_set1_epi64x(NEG_INF); __m128i vOpen = _mm_set1_epi64x(open); __m128i vGap = _mm_set1_epi64x(gap); __m128i vZero = _mm_set1_epi64x(0); __m128i vOne = _mm_set1_epi64x(1); __m128i vN = _mm_set1_epi64x(N); __m128i vGapN = _mm_set1_epi64x(gap*N); __m128i vNegOne = _mm_set1_epi64x(-1); __m128i vI = _mm_set_epi64x(0,1); __m128i vJreset = _mm_set_epi64x(0,-1); __m128i vMaxScore = vNegInf; __m128i vMaxMatch = vNegInf; __m128i vMaxSimilar = vNegInf; __m128i vMaxLength = vNegInf; __m128i vILimit = _mm_set1_epi64x(s1Len); __m128i vILimit1 = _mm_sub_epi64(vILimit, vOne); __m128i vJLimit = _mm_set1_epi64x(s2Len); __m128i vJLimit1 = _mm_sub_epi64(vJLimit, vOne); __m128i vIBoundary = _mm_set_epi64x( -open-0*gap, -open-1*gap); /* convert _s1 from char to int in range 0-23 */ for (i=0; i<s1Len; ++i) {
/* * Notice: * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST * numbers of DD bits */ static inline uint16_t _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts, uint8_t *split_packet) { volatile union i40e_rx_desc *rxdp; struct i40e_rx_entry *sw_ring; uint16_t nb_pkts_recd; int pos; uint64_t var; __m128i shuf_msk; uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl; __m128i crc_adjust = _mm_set_epi16( 0, 0, 0, /* ignore non-length fields */ -rxq->crc_len, /* sub crc on data_len */ 0, /* ignore high-16bits of pkt_len */ -rxq->crc_len, /* sub crc on pkt_len */ 0, 0 /* ignore pkt_type field */ ); /* * compile-time check the above crc_adjust layout is correct. * NOTE: the first field (lowest address) is given last in set_epi16 * call above. */ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) != offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4); RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) != offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8); __m128i dd_check, eop_check; /* nb_pkts shall be less equal than RTE_I40E_MAX_RX_BURST */ nb_pkts = RTE_MIN(nb_pkts, RTE_I40E_MAX_RX_BURST); /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */ nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP); /* Just the act of getting into the function from the application is * going to cost about 7 cycles */ rxdp = rxq->rx_ring + rxq->rx_tail; rte_prefetch0(rxdp); /* See if we need to rearm the RX queue - gives the prefetch a bit * of time to act */ if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH) i40e_rxq_rearm(rxq); /* Before we start moving massive data around, check to see if * there is actually a packet available */ if (!(rxdp->wb.qword1.status_error_len & rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT))) return 0; /* 4 packets DD mask */ dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL); /* 4 packets EOP mask */ eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL); /* mask to shuffle from desc. to mbuf */ shuf_msk = _mm_set_epi8( 7, 6, 5, 4, /* octet 4~7, 32bits rss */ 3, 2, /* octet 2~3, low 16 bits vlan_macip */ 15, 14, /* octet 15~14, 16 bits data_len */ 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */ 15, 14, /* octet 15~14, low 16 bits pkt_len */ 0xFF, 0xFF, /* pkt_type set as unknown */ 0xFF, 0xFF /*pkt_type set as unknown */ ); /* * Compile-time verify the shuffle mask * NOTE: some field positions already verified above, but duplicated * here for completeness in case of future modifications. */ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) != offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4); RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) != offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8); RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) != offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10); RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) != offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12); /* Cache is empty -> need to scan the buffer rings, but first move * the next 'n' mbufs into the cache */ sw_ring = &rxq->sw_ring[rxq->rx_tail]; /* A. load 4 packet in one loop * [A*. mask out 4 unused dirty field in desc] * B. copy 4 mbuf point from swring to rx_pkts * C. calc the number of DD bits among the 4 packets * [C*. extract the end-of-packet bit, if requested] * D. fill info. from desc to mbuf */ for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts; pos += RTE_I40E_DESCS_PER_LOOP, rxdp += RTE_I40E_DESCS_PER_LOOP) { __m128i descs[RTE_I40E_DESCS_PER_LOOP]; __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4; __m128i zero, staterr, sterr_tmp1, sterr_tmp2; /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */ __m128i mbp1; #if defined(RTE_ARCH_X86_64) __m128i mbp2; #endif /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */ mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]); /* Read desc statuses backwards to avoid race condition */ /* A.1 load 4 pkts desc */ descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3)); rte_compiler_barrier(); /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */ _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1); #if defined(RTE_ARCH_X86_64) /* B.1 load 2 64 bit mbuf points */ mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]); #endif descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2)); rte_compiler_barrier(); /* B.1 load 2 mbuf point */ descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1)); rte_compiler_barrier(); descs[0] = _mm_loadu_si128((__m128i *)(rxdp)); #if defined(RTE_ARCH_X86_64) /* B.2 copy 2 mbuf point into rx_pkts */ _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2); #endif if (split_packet) { rte_mbuf_prefetch_part2(rx_pkts[pos]); rte_mbuf_prefetch_part2(rx_pkts[pos + 1]); rte_mbuf_prefetch_part2(rx_pkts[pos + 2]); rte_mbuf_prefetch_part2(rx_pkts[pos + 3]); } /* avoid compiler reorder optimization */ rte_compiler_barrier(); /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/ const __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT); const __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT); /* merge the now-aligned packet length fields back in */ descs[3] = _mm_blend_epi16(descs[3], len3, 0x80); descs[2] = _mm_blend_epi16(descs[2], len2, 0x80); /* D.1 pkt 3,4 convert format from desc to pktmbuf */ pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk); pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk); /* C.1 4=>2 filter staterr info only */ sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]); /* C.1 4=>2 filter staterr info only */ sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]); desc_to_olflags_v(rxq, descs, &rx_pkts[pos]); /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */ pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust); pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust); /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/ const __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT); const __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT); /* merge the now-aligned packet length fields back in */ descs[1] = _mm_blend_epi16(descs[1], len1, 0x80); descs[0] = _mm_blend_epi16(descs[0], len0, 0x80); /* D.1 pkt 1,2 convert format from desc to pktmbuf */ pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk); pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk); /* C.2 get 4 pkts staterr value */ zero = _mm_xor_si128(dd_check, dd_check); staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2); /* D.3 copy final 3,4 data to rx_pkts */ _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1, pkt_mb4); _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1, pkt_mb3); /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */ pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust); pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust); /* C* extract and record EOP bit */ if (split_packet) { __m128i eop_shuf_mask = _mm_set_epi8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x04, 0x0C, 0x00, 0x08 ); /* and with mask to extract bits, flipping 1-0 */ __m128i eop_bits = _mm_andnot_si128(staterr, eop_check); /* the staterr values are not in order, as the count * count of dd bits doesn't care. However, for end of * packet tracking, we do care, so shuffle. This also * compresses the 32-bit values to 8-bit */ eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask); /* store the resulting 32-bit value */ *(int *)split_packet = _mm_cvtsi128_si32(eop_bits); split_packet += RTE_I40E_DESCS_PER_LOOP; } /* C.3 calc available number of desc */ staterr = _mm_and_si128(staterr, dd_check); staterr = _mm_packs_epi32(staterr, zero); /* D.3 copy final 1,2 data to rx_pkts */ _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1, pkt_mb2); _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1, pkt_mb1); desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl); /* C.4 calc avaialbe number of desc */ var = __builtin_popcountll(_mm_cvtsi128_si64(staterr)); nb_pkts_recd += var; if (likely(var != RTE_I40E_DESCS_PER_LOOP)) break; } /* Update our internal tail pointer */ rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd); rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1)); rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd); return nb_pkts_recd; }
static inline uint16_t fm10k_recv_raw_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts, uint8_t *split_packet) { volatile union fm10k_rx_desc *rxdp; struct rte_mbuf **mbufp; uint16_t nb_pkts_recd; int pos; struct fm10k_rx_queue *rxq = rx_queue; uint64_t var; __m128i shuf_msk; __m128i dd_check, eop_check; uint16_t next_dd; next_dd = rxq->next_dd; /* Just the act of getting into the function from the application is * going to cost about 7 cycles */ rxdp = rxq->hw_ring + next_dd; rte_prefetch0(rxdp); /* See if we need to rearm the RX queue - gives the prefetch a bit * of time to act */ if (rxq->rxrearm_nb > RTE_FM10K_RXQ_REARM_THRESH) fm10k_rxq_rearm(rxq); /* Before we start moving massive data around, check to see if * there is actually a packet available */ if (!(rxdp->d.staterr & FM10K_RXD_STATUS_DD)) return 0; /* Vecotr RX will process 4 packets at a time, strip the unaligned * tails in case it's not multiple of 4. */ nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_FM10K_DESCS_PER_LOOP); /* 4 packets DD mask */ dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL); /* 4 packets EOP mask */ eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL); /* mask to shuffle from desc. to mbuf */ shuf_msk = _mm_set_epi8( 7, 6, 5, 4, /* octet 4~7, 32bits rss */ 15, 14, /* octet 14~15, low 16 bits vlan_macip */ 13, 12, /* octet 12~13, 16 bits data_len */ 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */ 13, 12, /* octet 12~13, low 16 bits pkt_len */ 0xFF, 0xFF, /* skip high 16 bits pkt_type */ 0xFF, 0xFF /* Skip pkt_type field in shuffle operation */ ); /* * Compile-time verify the shuffle mask * NOTE: some field positions already verified above, but duplicated * here for completeness in case of future modifications. */ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) != offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4); RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) != offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8); RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) != offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10); RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) != offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12); /* Cache is empty -> need to scan the buffer rings, but first move * the next 'n' mbufs into the cache */ mbufp = &rxq->sw_ring[next_dd]; /* A. load 4 packet in one loop * [A*. mask out 4 unused dirty field in desc] * B. copy 4 mbuf point from swring to rx_pkts * C. calc the number of DD bits among the 4 packets * [C*. extract the end-of-packet bit, if requested] * D. fill info. from desc to mbuf */ for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts; pos += RTE_FM10K_DESCS_PER_LOOP, rxdp += RTE_FM10K_DESCS_PER_LOOP) { __m128i descs0[RTE_FM10K_DESCS_PER_LOOP]; __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4; __m128i zero, staterr, sterr_tmp1, sterr_tmp2; __m128i mbp1; /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */ #if defined(RTE_ARCH_X86_64) __m128i mbp2; #endif /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */ mbp1 = _mm_loadu_si128((__m128i *)&mbufp[pos]); /* Read desc statuses backwards to avoid race condition */ /* A.1 load 4 pkts desc */ descs0[3] = _mm_loadu_si128((__m128i *)(rxdp + 3)); rte_compiler_barrier(); /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */ _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1); #if defined(RTE_ARCH_X86_64) /* B.1 load 2 64 bit mbuf poitns */ mbp2 = _mm_loadu_si128((__m128i *)&mbufp[pos+2]); #endif descs0[2] = _mm_loadu_si128((__m128i *)(rxdp + 2)); rte_compiler_barrier(); /* B.1 load 2 mbuf point */ descs0[1] = _mm_loadu_si128((__m128i *)(rxdp + 1)); rte_compiler_barrier(); descs0[0] = _mm_loadu_si128((__m128i *)(rxdp)); #if defined(RTE_ARCH_X86_64) /* B.2 copy 2 mbuf point into rx_pkts */ _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2); #endif /* avoid compiler reorder optimization */ rte_compiler_barrier(); if (split_packet) { rte_mbuf_prefetch_part2(rx_pkts[pos]); rte_mbuf_prefetch_part2(rx_pkts[pos + 1]); rte_mbuf_prefetch_part2(rx_pkts[pos + 2]); rte_mbuf_prefetch_part2(rx_pkts[pos + 3]); } /* D.1 pkt 3,4 convert format from desc to pktmbuf */ pkt_mb4 = _mm_shuffle_epi8(descs0[3], shuf_msk); pkt_mb3 = _mm_shuffle_epi8(descs0[2], shuf_msk); /* C.1 4=>2 filter staterr info only */ sterr_tmp2 = _mm_unpackhi_epi32(descs0[3], descs0[2]); /* C.1 4=>2 filter staterr info only */ sterr_tmp1 = _mm_unpackhi_epi32(descs0[1], descs0[0]); /* set ol_flags with vlan packet type */ fm10k_desc_to_olflags_v(descs0, &rx_pkts[pos]); /* D.1 pkt 1,2 convert format from desc to pktmbuf */ pkt_mb2 = _mm_shuffle_epi8(descs0[1], shuf_msk); pkt_mb1 = _mm_shuffle_epi8(descs0[0], shuf_msk); /* C.2 get 4 pkts staterr value */ zero = _mm_xor_si128(dd_check, dd_check); staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2); /* D.3 copy final 3,4 data to rx_pkts */ _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1, pkt_mb4); _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1, pkt_mb3); /* C* extract and record EOP bit */ if (split_packet) { __m128i eop_shuf_mask = _mm_set_epi8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x04, 0x0C, 0x00, 0x08 ); /* and with mask to extract bits, flipping 1-0 */ __m128i eop_bits = _mm_andnot_si128(staterr, eop_check); /* the staterr values are not in order, as the count * count of dd bits doesn't care. However, for end of * packet tracking, we do care, so shuffle. This also * compresses the 32-bit values to 8-bit */ eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask); /* store the resulting 32-bit value */ *(int *)split_packet = _mm_cvtsi128_si32(eop_bits); split_packet += RTE_FM10K_DESCS_PER_LOOP; /* zero-out next pointers */ rx_pkts[pos]->next = NULL; rx_pkts[pos + 1]->next = NULL; rx_pkts[pos + 2]->next = NULL; rx_pkts[pos + 3]->next = NULL; } /* C.3 calc available number of desc */ staterr = _mm_and_si128(staterr, dd_check); staterr = _mm_packs_epi32(staterr, zero); /* D.3 copy final 1,2 data to rx_pkts */ _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1, pkt_mb2); _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1, pkt_mb1); fm10k_desc_to_pktype_v(descs0, &rx_pkts[pos]); /* C.4 calc avaialbe number of desc */ var = __builtin_popcountll(_mm_cvtsi128_si64(staterr)); nb_pkts_recd += var; if (likely(var != RTE_FM10K_DESCS_PER_LOOP)) break; } /* Update our internal tail pointer */ rxq->next_dd = (uint16_t)(rxq->next_dd + nb_pkts_recd); rxq->next_dd = (uint16_t)(rxq->next_dd & (rxq->nb_desc - 1)); rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd); return nb_pkts_recd; }
static inline void ixgbe_rxq_rearm(struct igb_rx_queue *rxq) { int i; uint16_t rx_id; volatile union ixgbe_adv_rx_desc *rxdp; struct igb_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start]; struct rte_mbuf *mb0, *mb1; __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM, RTE_PKTMBUF_HEADROOM); __m128i dma_addr0, dma_addr1; rxdp = rxq->rx_ring + rxq->rxrearm_start; /* Pull 'n' more MBUFs into the software ring */ if (rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep, RTE_IXGBE_RXQ_REARM_THRESH) < 0) { if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >= rxq->nb_rx_desc) { dma_addr0 = _mm_setzero_si128(); for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) { rxep[i].mbuf = &rxq->fake_mbuf; _mm_store_si128((__m128i *)&rxdp[i].read, dma_addr0); } } return; } /* Initialize the mbufs in vector, process 2 mbufs in one loop */ for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) { __m128i vaddr0, vaddr1; mb0 = rxep[0].mbuf; mb1 = rxep[1].mbuf; /* flush mbuf with pkt template */ mb0->rearm_data[0] = rxq->mbuf_initializer; mb1->rearm_data[0] = rxq->mbuf_initializer; /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */ vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr)); vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr)); /* convert pa to dma_addr hdr/data */ dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0); dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1); /* add headroom to pa values */ dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room); dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room); /* flush desc with pa dma_addr */ _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0); _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1); } rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH; if (rxq->rxrearm_start >= rxq->nb_rx_desc) rxq->rxrearm_start = 0; rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH; rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ? (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1)); /* Update the tail pointer on the NIC */ IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id); }
rxq->rxrearm_start = 0; rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH; rx_id = (uint16_t)((rxq->rxrearm_start == 0) ? (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1)); /* Update the tail pointer on the NIC */ I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id); } static inline void desc_to_olflags_v(struct i40e_rx_queue *rxq, __m128i descs[4] __rte_unused, struct rte_mbuf **rx_pkts) { const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer); __m128i rearm0, rearm1, rearm2, rearm3; __m128i vlan0, vlan1, rss, l3_l4e; /* mask everything except RSS, flow director and VLAN flags * bit2 is for VLAN tag, bit11 for flow director indication * bit13:12 for RSS indication. */ const __m128i rss_vlan_msk = _mm_set_epi32( 0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804); const __m128i cksum_mask = _mm_set_epi32( PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD | PKT_RX_EIP_CKSUM_BAD,
/* * vPMD raw receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP) * * Notice: * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST * numbers of DD bit * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two * - don't support ol_flags for rss and csum err */ static inline uint16_t _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts, uint8_t *split_packet) { volatile union ixgbe_adv_rx_desc *rxdp; struct ixgbe_rx_entry *sw_ring; uint16_t nb_pkts_recd; int pos; uint64_t var; __m128i shuf_msk; __m128i crc_adjust = _mm_set_epi16( 0, 0, 0, /* ignore non-length fields */ -rxq->crc_len, /* sub crc on data_len */ 0, /* ignore high-16bits of pkt_len */ -rxq->crc_len, /* sub crc on pkt_len */ 0, 0 /* ignore pkt_type field */ ); __m128i dd_check, eop_check; /* nb_pkts shall be less equal than RTE_IXGBE_MAX_RX_BURST */ nb_pkts = RTE_MIN(nb_pkts, RTE_IXGBE_MAX_RX_BURST); /* nb_pkts has to be floor-aligned to RTE_IXGBE_DESCS_PER_LOOP */ nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_IXGBE_DESCS_PER_LOOP); /* Just the act of getting into the function from the application is * going to cost about 7 cycles */ rxdp = rxq->rx_ring + rxq->rx_tail; _mm_prefetch((const void *)rxdp, _MM_HINT_T0); /* See if we need to rearm the RX queue - gives the prefetch a bit * of time to act */ if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH) ixgbe_rxq_rearm(rxq); /* Before we start moving massive data around, check to see if * there is actually a packet available */ if (!(rxdp->wb.upper.status_error & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) return 0; /* 4 packets DD mask */ dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL); /* 4 packets EOP mask */ eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL); /* mask to shuffle from desc. to mbuf */ shuf_msk = _mm_set_epi8( 7, 6, 5, 4, /* octet 4~7, 32bits rss */ 15, 14, /* octet 14~15, low 16 bits vlan_macip */ 13, 12, /* octet 12~13, 16 bits data_len */ 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */ 13, 12, /* octet 12~13, low 16 bits pkt_len */ 0xFF, 0xFF, /* skip 32 bit pkt_type */ 0xFF, 0xFF ); /* Cache is empty -> need to scan the buffer rings, but first move * the next 'n' mbufs into the cache */ sw_ring = &rxq->sw_ring[rxq->rx_tail]; /* A. load 4 packet in one loop * [A*. mask out 4 unused dirty field in desc] * B. copy 4 mbuf point from swring to rx_pkts * C. calc the number of DD bits among the 4 packets * [C*. extract the end-of-packet bit, if requested] * D. fill info. from desc to mbuf */ for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts; pos += RTE_IXGBE_DESCS_PER_LOOP, rxdp += RTE_IXGBE_DESCS_PER_LOOP) { __m128i descs[RTE_IXGBE_DESCS_PER_LOOP]; __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4; __m128i zero, staterr, sterr_tmp1, sterr_tmp2; __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */ /* B.1 load 1 mbuf point */ mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]); /* Read desc statuses backwards to avoid race condition */ /* A.1 load 4 pkts desc */ descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3)); /* B.2 copy 2 mbuf point into rx_pkts */ _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1); /* B.1 load 1 mbuf point */ mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]); descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2)); /* B.1 load 2 mbuf point */ descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1)); descs[0] = _mm_loadu_si128((__m128i *)(rxdp)); /* B.2 copy 2 mbuf point into rx_pkts */ _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2); if (split_packet) { rte_mbuf_prefetch_part2(rx_pkts[pos]); rte_mbuf_prefetch_part2(rx_pkts[pos + 1]); rte_mbuf_prefetch_part2(rx_pkts[pos + 2]); rte_mbuf_prefetch_part2(rx_pkts[pos + 3]); } /* avoid compiler reorder optimization */ rte_compiler_barrier(); /* D.1 pkt 3,4 convert format from desc to pktmbuf */ pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk); pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk); /* D.1 pkt 1,2 convert format from desc to pktmbuf */ pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk); pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk); /* C.1 4=>2 filter staterr info only */ sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]); /* C.1 4=>2 filter staterr info only */ sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]); /* set ol_flags with vlan packet type */ desc_to_olflags_v(descs, &rx_pkts[pos]); /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */ pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust); pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust); /* C.2 get 4 pkts staterr value */ zero = _mm_xor_si128(dd_check, dd_check); staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2); /* D.3 copy final 3,4 data to rx_pkts */ _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1, pkt_mb4); _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1, pkt_mb3); /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */ pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust); pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust); /* C* extract and record EOP bit */ if (split_packet) { __m128i eop_shuf_mask = _mm_set_epi8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x04, 0x0C, 0x00, 0x08 ); /* and with mask to extract bits, flipping 1-0 */ __m128i eop_bits = _mm_andnot_si128(staterr, eop_check); /* the staterr values are not in order, as the count * count of dd bits doesn't care. However, for end of * packet tracking, we do care, so shuffle. This also * compresses the 32-bit values to 8-bit */ eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask); /* store the resulting 32-bit value */ *(int *)split_packet = _mm_cvtsi128_si32(eop_bits); split_packet += RTE_IXGBE_DESCS_PER_LOOP; /* zero-out next pointers */ rx_pkts[pos]->next = NULL; rx_pkts[pos + 1]->next = NULL; rx_pkts[pos + 2]->next = NULL; rx_pkts[pos + 3]->next = NULL; } /* C.3 calc available number of desc */ staterr = _mm_and_si128(staterr, dd_check); staterr = _mm_packs_epi32(staterr, zero); /* D.3 copy final 1,2 data to rx_pkts */ _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1, pkt_mb2); _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1, pkt_mb1); /* C.4 calc avaialbe number of desc */ var = __builtin_popcountll(_mm_cvtsi128_si64(staterr)); nb_pkts_recd += var; if (likely(var != RTE_IXGBE_DESCS_PER_LOOP)) break; } /* Update our internal tail pointer */ rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd); rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1)); rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd); return nb_pkts_recd; }
static void read_data(FILE * data_input) { char line_buffer[4096], *tmp; int line; tmp = fgets(line_buffer, 4096, data_input); assert(tmp == line_buffer); if (sscanf (line_buffer, "%d %d %d %d " "%d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d " "%d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d", &num_data, &num_to_output, &num_words, &max_dist, score_factors + 0, score_factors + 1, score_factors + 2, score_factors + 3, score_factors + 4, score_factors + 5, score_factors + 6, score_factors + 7, score_factors + 8, score_factors + 9, score_factors + 10, score_factors + 11, score_factors + 12, score_factors + 13, score_factors + 14, score_factors + 15, score_factors + 16, score_factors + 17, score_factors + 18, score_factors + 19, score_factors + 20, score_factors + 21, score_factors + 22, score_factors + 23, score_factors + 24, score_factors + 25, score_factors + 26, score_factors + 27, score_factors + 28, score_factors + 29, score_factors + 30, score_factors + 31) != 4 + 32) { usage("wrong number of parameters in first line"); } assert(max_dist > 0); assert(num_words == 1 || num_words == 3); data = malloc(sizeof(__m128i) * num_data * num_words); available = malloc(sizeof(char) * num_data); to_output = malloc(sizeof(char) * num_data); memset(to_output, 0, sizeof(char) * num_data); counters = malloc(sizeof(counter_t) * num_data * NUM_SCORES); memset(counters, 0, sizeof(counter_t) * num_data * NUM_SCORES); assert(num_to_output <= num_data); assert(max_dist <= NUM_SCORES); for (int i = 0; i < NUM_SCORES; i++) { assert(score_factors[i] > 0); if (i > max_dist) { score_factors[i] = 0; } else { assert(score_factors[i] > 0); } } if (num_words == 1) { diff_percent = diff_percent_gray; } else { diff_percent = diff_percent_rgb; } for (line = 0; line < num_data; line++) { tmp = fgets(line_buffer, 4096, data_input); assert(tmp == line_buffer); if (strncmp(line_buffer, "na", 2) == 0) { available[line] = 0; if (num_words == 1) data[line] = _mm_set_epi64x(line, line); else { data[3 * line] = _mm_set_epi64x(line, line); data[3 * line + 1] = _mm_set_epi64x(line, line); data[3 * line + 2] = _mm_set_epi64x(line, line); } } else { available[line] = 1; // printf("len=%ld s='%s'\n", strlen(line_buffer), line_buffer); if (num_words == 1) { assert(strlen(line_buffer) == 32 + 1); // remove newline line_buffer[strlen(line_buffer) - 1] = '\0'; __m128i val = simple_strtoul(line_buffer); data[line] = val; } else { assert(strlen(line_buffer) == num_words * (32 + 1) - 1 + 1); // remove newline line_buffer[strlen(line_buffer) - 1] = '\0'; assert(line_buffer[32] == ' '); assert(line_buffer[64 + 1] == ' '); __m128i val1 = simple_strtoul(line_buffer); __m128i val2 = simple_strtoul(line_buffer + 32 + 1); __m128i val3 = simple_strtoul(line_buffer + 64 + 2); data[3 * line] = val1; data[3 * line + 1] = val2; data[3 * line + 2] = val3; } } // printf("line=%d = '%s' = %lx avail=%d\n", line, line_buffer, (*data)[line], (*available)[line]); } }
static inline void ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq) { int i; uint16_t rx_id; volatile union ixgbe_adv_rx_desc *rxdp; struct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start]; struct rte_mbuf *mb0, *mb1; __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM, RTE_PKTMBUF_HEADROOM); __m128i dma_addr0, dma_addr1; const __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX); rxdp = rxq->rx_ring + rxq->rxrearm_start; /* Pull 'n' more MBUFs into the software ring */ if (rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep, RTE_IXGBE_RXQ_REARM_THRESH) < 0) { if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >= rxq->nb_rx_desc) { dma_addr0 = _mm_setzero_si128(); for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) { rxep[i].mbuf = &rxq->fake_mbuf; _mm_store_si128((__m128i *)&rxdp[i].read, dma_addr0); } } rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed += RTE_IXGBE_RXQ_REARM_THRESH; return; } /* Initialize the mbufs in vector, process 2 mbufs in one loop */ for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) { __m128i vaddr0, vaddr1; uintptr_t p0, p1; mb0 = rxep[0].mbuf; mb1 = rxep[1].mbuf; /* * Flush mbuf with pkt template. * Data to be rearmed is 6 bytes long. * Though, RX will overwrite ol_flags that are coming next * anyway. So overwrite whole 8 bytes with one load: * 6 bytes of rearm_data plus first 2 bytes of ol_flags. */ p0 = (uintptr_t)&mb0->rearm_data; *(uint64_t *)p0 = rxq->mbuf_initializer; p1 = (uintptr_t)&mb1->rearm_data; *(uint64_t *)p1 = rxq->mbuf_initializer; /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */ vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr)); vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr)); /* convert pa to dma_addr hdr/data */ dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0); dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1); /* add headroom to pa values */ dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room); dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room); /* set Header Buffer Address to zero */ dma_addr0 = _mm_and_si128(dma_addr0, hba_msk); dma_addr1 = _mm_and_si128(dma_addr1, hba_msk); /* flush desc with pa dma_addr */ _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0); _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1); } rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH; if (rxq->rxrearm_start >= rxq->nb_rx_desc) rxq->rxrearm_start = 0; rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH; rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ? (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1)); /* Update the tail pointer on the NIC */ IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id); }
/* * Simulates an implementation of a * Littlun-like cipher many times, for speed * evaluation */ __m128i dummy_cipher_eval() { __m128i x, k; unsigned long long tick1, tick2, dum; x = _mm_set_epi64x(0x0001020304050607, 0x08090a0b0c0d0e0f); k = _mm_set_epi64x(0x0a030d0c0f050607, 0x08090a000c0d0e0f); dum = 0; for (tick1 = 0; tick1 < 1ull << 31; tick1++) dum += 2*tick1 & (~tick1 | (tick1 >> 2)); x = SB(x); x = M128(x); x = SB(x); x = M128(x); x = SB(x); x = M128(x); x = SB(x); x = M128(x); x = SB(x); x = M128(x); x = SB(x); x = M128(x); x = SB(x); x = M128(x); x = SB(x); x = M128(x); x = SB(x); x = M128(x); x = SB(x); x = M128(x); x = SB(x); x = M128(x); x = SB(x); x = M128(x); x = SB(x); x = M128(x); x = SB(x); x = M128(x); x = SB(x); x = M128(x); x = SB(x); x = M128(x); tick1 = rdtsc(); // // r1 // x = _mm_xor_si128(x,k); // x = SB(x); // x = M128(x); // // r2 // x = _mm_xor_si128(x,k); // x = SB(x); // x = M128(x); // // r3 // x = _mm_xor_si128(x,k); // x = SB(x); // x = M128(x); // // r4 // x = _mm_xor_si128(x,k); // x = SB(x); // x = M128(x); // // r5 // x = _mm_xor_si128(x,k); // x = SB(x); // x = M128(x); // // r6 // x = _mm_xor_si128(x,k); // x = SB(x); // x = M128(x); // // r7 // x = _mm_xor_si128(x,k); // x = SB(x); // x = M128(x); // // r8 // x = _mm_xor_si128(x,k); // x = SB(x); // x = M128(x); // // final // x = _mm_xor_si128(x,k); tick2 = rdtsc(); printf("%llu ~ %llu cycles\n\n", dum, tick2 - tick1); return x; }