static void set_led_f(int pf, int state)
{
	switch (state) {
		case STATUS_LED_OFF:      bfin_write_PORTFIO_CLEAR(pf);  break;
		case STATUS_LED_BLINKING: bfin_write_PORTFIO_TOGGLE(pf); break;
		case STATUS_LED_ON:       bfin_write_PORTFIO_SET(pf);    break;
	}
}
void board_reset(void)
{
	/* workaround for weak pull ups on ssel */
	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
		bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10);
		bfin_write_PORTFIO_SET(PF10);
		udelay(1);
	}
}
示例#3
0
u8 bfspi_read_8_bits(u16 chip_select)
{
  u16 flag_enable, flag;
  u8 ret;

  if (chip_select < 8) {
    flag = bfin_read_SPI_FLG();
    flag_enable = flag & ~(1 << (chip_select + 8));
    //PRINTK("read: flag: 0x%04x flag_enable: 0x%04x \n", flag, flag_enable);
  }
  else {
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
    bfin_write_FIO_FLAG_C((1<<chip_select)); 
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
        bfin_write_PORTFIO_CLEAR((1<<chip_select));
#endif
    __builtin_bfin_ssync();
  }

  /* drop SPISEL */
  bfin_write_SPI_FLG(flag_enable); 

  /* read kicks off transfer, detect end by polling RXS, we
     read the shadow register to prevent another transfer
     being started 

     While reading we write a dummy tx value, 0xff.  For
     the MMC card, a 0 bit indicates the start of a command 
     sequence therefore an all 1's sequence keeps the MMC
     card in the current state.
  */
  bfin_write_SPI_TDBR(0xff);
  bfin_read_SPI_RDBR(); __builtin_bfin_ssync();
  do { } while (!(bfin_read_SPI_STAT() & RXS)); //hardcode RXS mask
  ret = bfin_read_SPI_SHADOW(); __builtin_bfin_ssync();

  //ret = read_RDBR(); __builtin_bfin_ssync();
  PRINTK("\nkern>> read: 0x%04X\n", ret);	
  /* raise SPISEL */
  if (chip_select < 8) {
    bfin_write_SPI_FLG(flag); 
  }
  else {
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
    bfin_write_FIO_FLAG_S((1<<chip_select)); 
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
        bfin_write_PORTFIO_SET((1<<chip_select));
#endif
    __builtin_bfin_ssync();
  }

  return ret;
}
示例#4
0
void bfspi_write_8_bits(u16 chip_select, u8 bits)
{
  u16 flag_enable, flag;

  if (chip_select < 8) {
    flag = bfin_read_SPI_FLG();
    flag_enable = flag & ~(1 << (chip_select + 8));
    //PRINTK("kern>> chip_select: %d write: flag: 0x%04x flag_enable: 0x%04x \n", chip_select, flag, flag_enable);

    /* drop SPISEL */
    bfin_write_SPI_FLG(flag_enable); 
  }
  else {
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
  	bfin_write_FIO_FLAG_C((1<<chip_select)); 
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
	bfin_write_PORTFIO_CLEAR((1<<chip_select));
#endif
  	__builtin_bfin_ssync();
  }

  /* read kicks off transfer, detect end by polling RXS */
  
  bfin_write_SPI_TDBR(bits);
  bfin_read_SPI_RDBR(); __builtin_bfin_ssync();
  do {} while (!(bfin_read_SPI_STAT() & RXS)); //hardcode RXS mask
  //(void) bfin_read_SPI_SHADOW(); //discard data && clear rxs
  //__builtin_bfin_ssync();
  
  /* raise SPISEL */
  if (chip_select < 8) {
    bfin_write_SPI_FLG(flag); 
  }
  else {
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
    bfin_write_FIO_FLAG_S((1<<chip_select)); 
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
        bfin_write_PORTFIO_SET((1<<chip_select));
#endif
    __builtin_bfin_ssync();
  }
}
示例#5
0
void bfspi_reset(int reset_bit) {
	PRINTK("toggle reset\n");
  
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
       	PRINTK("set reset to PF%d\n",reset_bit);
  	bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (1<<reset_bit)); 
  	__builtin_bfin_ssync();

  	bfin_write_FIO_FLAG_C((1<<reset_bit)); 
  	__builtin_bfin_ssync();
  	udelay(100);

  	bfin_write_FIO_FLAG_S((1<<reset_bit));
  	__builtin_bfin_ssync();
#endif
  	
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
	if (reset_bit == 1) {
       		PRINTK("set reset to PF10\n");
                bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFBFF);
		__builtin_bfin_ssync();
		bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0400);
		__builtin_bfin_ssync();
		bfin_write_PORTFIO_CLEAR(1<<10);
		__builtin_bfin_ssync();
		udelay(100);
		bfin_write_PORTFIO_SET(1<<10);
		__builtin_bfin_ssync();
        } else if (reset_bit == 2)  {
                PRINTK("Error: cannot set reset to PJ11\n");
        } else if (reset_bit == 3) {
                PRINTK("Error: cannot set reset to PJ10\n");
        } else if (reset_bit == 4) {
                PRINTK("set reset to PF6\n");
                bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFFBF);
                __builtin_bfin_ssync();
		bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0040);
		__builtin_bfin_ssync();
		bfin_write_PORTFIO_CLEAR(1<<6);
		__builtin_bfin_ssync();
		udelay(100);
		bfin_write_PORTFIO_SET(1<<6);
		__builtin_bfin_ssync();
        } else if (reset_bit == 5) {
                PRINTK("set reset to PF5\n");
                bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFFDF);
                __builtin_bfin_ssync();
		bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0020);
		__builtin_bfin_ssync();
		bfin_write_PORTFIO_CLEAR(1<<5);
		__builtin_bfin_ssync();
		udelay(100);
		bfin_write_PORTFIO_SET(1<<5);
		__builtin_bfin_ssync();
        } else if (reset_bit == 6) {
                PRINTK("set reset to PF4\n");
                bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFFEF);
                __builtin_bfin_ssync();
		bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0010);
		__builtin_bfin_ssync();
		bfin_write_PORTFIO_CLEAR(1<<4);
		__builtin_bfin_ssync();
		udelay(100);
		bfin_write_PORTFIO_SET(1<<4);
		__builtin_bfin_ssync();
        } else if (reset_bit == 7) {
                PRINTK("Error: cannot set reset to PJ5\n");

		} else if (reset_bit == 8) {

			PRINTK("Using PF8 for reset...\n");
			bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFEFF);
			__builtin_bfin_ssync();
			bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0100);
			__builtin_bfin_ssync();
			bfin_write_PORTFIO_CLEAR(1<<8);
			__builtin_bfin_ssync();
			udelay(100);
			bfin_write_PORTFIO_SET(1<<8);

		} else if ( reset_bit == 9 ) {
			PRINTK("Using PF9 for reset...\n");
			bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFDFF);
			__builtin_bfin_ssync();
			bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0200);
			__builtin_bfin_ssync();
			bfin_write_PORTFIO_CLEAR(1<<9);
			__builtin_bfin_ssync();
			udelay(100);
			bfin_write_PORTFIO_SET(1<<9);


		}

#endif	
  /* 
     p24 3050 data sheet, allow 1ms for PLL lock, with
     less than 1ms (1000us) I found register 2 would have
     a value of 0 rather than 3, indicating a bad reset.
  */
  udelay(1000); 
}