示例#1
0
文件: vgatest.c 项目: skeezix/zikzak
void tim2_isr ( void ) {

  //TIM2_SR &= ~TIM_SR_UIF;    //clearing update interrupt flag
  TIM_SR(TIM2) &= ~TIM_SR_UIF; /* Clear interrrupt flag. */

  /* ISR HAS TO DO SOMRTHING A LITTLE HEAVY
  // https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Problem%20with%20DMA-USART%20Rx%20on%20STM32F407VG&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=148
  // ie: after setting SR, you need to pause read/writes
  // ie: if the ISR is too quick, there may be a spurious re-invocation (tail chain), so you need to do a little something to avoid cpu race condition
  // -- another way to do it, is to do a SR read (which blocks until its 'set' finishes), thus stalling until the ISR is 'done':
  //void SPI2_IRQHandler(void)                                                                                                                                                              {                                                                                                                                                                                         volatile unsigned int dummy;                                                                                                                                                         ... some code...                                                                                                                                                                              SPI2_CR2 &= ~SPI_CR2_RXNEIE;  // Turn off RXE interrupt enable                                                                                                                    ...some code...                                                                                                                                                                              dummy = SPI2_SR; // Prevent tail-chaining.                                                                                                                                            return;                                                                                                                                                                        }         
  */
#if 0
  __asm__("nop");
  gpio_toggle(GPIOB, GPIO12); /* LED on/off. */
#endif


  // VGA line logic
  //
  // line1
  // line2
  // ..
  // line600
  // front porch blank            1 line
  // vsync pulse                  4 lines
  // back porch blank             23 lines
  // \__> back to top
  //

  // handle vblank stuff
  // - front porch, leads to
  //  - vsync, leads to
  //   - back porch
  // vsync is normally HIGH, but goes to LOW during pulse
  done_sync = 0;
  if ( front_porch_togo ) {
    front_porch_togo --;

    if ( ! front_porch_togo ) { // on exit front porch, start vsync pulse
      vsync_go_low();
      vsync_togo = 4;
    }

    done_sync = 1;
    goto hsync;
    //return; // do nothing..
  }

  if ( vsync_togo ) {
    vsync_togo --;

    if ( ! vsync_togo ) { // on exit vsync pulse, start back porch
      vsync_go_high();
      back_porch_togo = 23;
    }

    done_sync = 1;
    goto hsync;
    //return;
  }

  if ( back_porch_togo ) {
    back_porch_togo --;

    if ( ! back_porch_togo ) {
      line_count = 1;
    }

    done_sync = 1;
    goto hsync;
    //return; // do nothing..
  }

 hsync:
  // hsync period..
  // should use timer/interupt to 'end the line' and go hsync?
  //

  /* 1uS Front Porch */
  /* 1uS */
  i = 22;
  while ( i-- ) {
    __asm__("nop");
  }

  /* 3.2uS Horizontal Sync */
  hsync_go_low();
  i = 60;
  while ( i-- ) {
    __asm__("nop");
  }

  /* 2.2uS Back Porch */
  hsync_go_high();
  i = 45;
  while ( i-- ) {
    __asm__("nop");
  }

  if ( done_sync ) {
    return;
  }




  // actual line data
  //
  // line data on/off/on/off..
  // off for hsync/porch business!

#if 1 // pull from array
  //i = line_count % FBHEIGHT;
  i = line_count/4;
  unsigned char *p = framebuffer + ( i * FBWIDTH ); // 240
  //p = framebuffer + ( (line_count%240) * 240 );

#if 1
  dma_memcpy ( p, 320 );
#else
  i = 90 / 10; // 120
  while ( i-- ) {

    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );

    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );
    rgb_go_level ( (*p++) );

    //gpio_set ( GPIOC, *p++ );
    //GPIO_BSRR(GPIOC) = *p++;
    //GPIO_BSRR(GPIOC) = 1<<6;
  }

  // disable all colour pins (dma does it itself in its isr)
  //GPIO_BSRR(GPIOC) = 0x00;
  gpio_clear ( GPIOC, GPIO0 | GPIO1 | GPIO2 | GPIO3 | GPIO4 | GPIO5 );
  //rgb_go_level ( 0 );

#endif

#endif

  // entering vblank period?
  //

  if ( line_count > VISIBLE_ROWS ) {
    front_porch_togo = 1;
    return; // entering front porch
  }

  line_count++;
}
示例#2
0
static int __sram spi_transfer_step(struct spi_stellaris_data *priv)
{
  dev_vdbg(&priv->bitbang.master->dev, "%s: ntxwords %d, nrxwords %d, nwords %d, SR %08x\n",
          __func__, priv->ntxwords, priv->nrxwords, priv->nwords,
          ssi_getreg(priv, STLR_SSI_SR_OFFSET));

#ifdef CONFIG_STELLARIS_DMA
		/* Check if the transfer is complete */
  if (priv->ntxwords == 0)
  {
		dev_dbg(&priv->bitbang.master->dev, "Transfer complete\n");
    /* Wake up the waiting thread */
    complete(&priv->xfer_done);
    return 0;
  }

	priv->xfer_size = min(priv->ntxwords, DMA_MAX_TRANSFER_SIZE);

	if( priv->txbuffer )
	{
		dma_memcpy(priv->dma_tx_buffer, priv->txbuffer, priv->xfer_size);
		priv->txbuffer = (char*)priv->txbuffer + priv->xfer_size;
	}

	dev_vdbg(&priv->bitbang.master->dev, "%s: xfer_size %u\n", __func__, priv->xfer_size);

	dma_setup_xfer(priv->dma_rx_channel, priv->dma_rx_buffer,
								 priv->base + STLR_SSI_DR_OFFSET, priv->xfer_size, priv->dma_rx_flags);
	dma_setup_xfer(priv->dma_tx_channel, priv->base + STLR_SSI_DR_OFFSET,
								 priv->dma_tx_buffer, priv->xfer_size, priv->dma_tx_flags);
	dma_start_xfer(priv->dma_rx_channel);
	dma_start_xfer(priv->dma_tx_channel);
#ifdef CONFIG_ARCH_TM4C
	putreg32(SSI_DMACTL_RXDMAE | SSI_DMACTL_TXDMAE, priv->base + STLR_SSI_DMACTL_OFFSET);
#endif /* CONFIG_ARCH_TM4C */
#else /* CONFIG_STELLARIS_DMA */
  /* Handle outgoing Tx FIFO transfers */
  ssi_performtx(priv);

  /* Handle incoming Rx FIFO transfers */
  ssi_performrx(priv);

  dev_vdbg(&priv->bitbang.master->dev, "ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
          priv->ntxwords, priv->nrxwords, priv->nwords,
          ssi_getreg(priv, STLR_SSI_SR_OFFSET),
          ssi_getreg(priv, STLR_SSI_IM_OFFSET));

	/* Check if the transfer is complete */
  if (priv->nrxwords >= priv->nwords)
  {
#ifndef POLLING_MODE
    /* Yes.. Disable all SSI interrupt sources */
    ssi_putreg(priv, STLR_SSI_IM_OFFSET, 0);

    /* Wake up the waiting thread */
    complete(&priv->xfer_done);
#endif /* POLLING_MODE */

    dev_dbg(&priv->bitbang.master->dev, "Transfer complete\n");

    return 0;
  }
#endif /* CONFIG_STELLARIS_DMA */

  return 1;
}
示例#3
0
/* Transfer the section to the L1 memory */
int
module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
			  char *secstrings, struct module *mod)
{
	/*
	 * XXX: sechdrs are vmalloced in kernel/module.c
	 * and would be vfreed just after module is loaded,
	 * so we hack to keep the only information we needed
	 * in mod->arch to correctly free L1 I/D sram later.
	 * NOTE: this breaks the semantic of mod->arch structure.
	 */
	Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
	void *dest;

	for (s = sechdrs; s < sechdrs_end; ++s) {
		const char *shname = secstrings + s->sh_name;

		if (s->sh_size == 0)
			continue;

		if (!strcmp(".l1.text", shname) ||
		    (!strcmp(".text", shname) &&
		     (hdr->e_flags & EF_BFIN_CODE_IN_L1))) {

			dest = l1_inst_sram_alloc(s->sh_size);
			mod->arch.text_l1 = dest;
			if (dest == NULL) {
				pr_err("L1 inst memory allocation failed\n",
					mod->name);
				return -1;
			}
			dma_memcpy(dest, (void *)s->sh_addr, s->sh_size);

		} else if (!strcmp(".l1.data", shname) ||
		           (!strcmp(".data", shname) &&
		            (hdr->e_flags & EF_BFIN_DATA_IN_L1))) {

			dest = l1_data_sram_alloc(s->sh_size);
			mod->arch.data_a_l1 = dest;
			if (dest == NULL) {
				pr_err("L1 data memory allocation failed\n",
					mod->name);
				return -1;
			}
			memcpy(dest, (void *)s->sh_addr, s->sh_size);

		} else if (!strcmp(".l1.bss", shname) ||
		           (!strcmp(".bss", shname) &&
		            (hdr->e_flags & EF_BFIN_DATA_IN_L1))) {

			dest = l1_data_sram_zalloc(s->sh_size);
			mod->arch.bss_a_l1 = dest;
			if (dest == NULL) {
				pr_err("L1 data memory allocation failed\n",
					mod->name);
				return -1;
			}

		} else if (!strcmp(".l1.data.B", shname)) {

			dest = l1_data_B_sram_alloc(s->sh_size);
			mod->arch.data_b_l1 = dest;
			if (dest == NULL) {
				pr_err("L1 data memory allocation failed\n",
					mod->name);
				return -1;
			}
			memcpy(dest, (void *)s->sh_addr, s->sh_size);

		} else if (!strcmp(".l1.bss.B", shname)) {

			dest = l1_data_B_sram_alloc(s->sh_size);
			mod->arch.bss_b_l1 = dest;
			if (dest == NULL) {
				pr_err("L1 data memory allocation failed\n",
					mod->name);
				return -1;
			}
			memset(dest, 0, s->sh_size);

		} else if (!strcmp(".l2.text", shname) ||
		           (!strcmp(".text", shname) &&
		            (hdr->e_flags & EF_BFIN_CODE_IN_L2))) {

			dest = l2_sram_alloc(s->sh_size);
			mod->arch.text_l2 = dest;
			if (dest == NULL) {
				pr_err("L2 SRAM allocation failed\n",
					mod->name);
				return -1;
			}
			memcpy(dest, (void *)s->sh_addr, s->sh_size);

		} else if (!strcmp(".l2.data", shname) ||
		           (!strcmp(".data", shname) &&
		            (hdr->e_flags & EF_BFIN_DATA_IN_L2))) {

			dest = l2_sram_alloc(s->sh_size);
			mod->arch.data_l2 = dest;
			if (dest == NULL) {
				pr_err("L2 SRAM allocation failed\n",
					mod->name);
				return -1;
			}
			memcpy(dest, (void *)s->sh_addr, s->sh_size);

		} else if (!strcmp(".l2.bss", shname) ||
		           (!strcmp(".bss", shname) &&
		            (hdr->e_flags & EF_BFIN_DATA_IN_L2))) {

			dest = l2_sram_zalloc(s->sh_size);
			mod->arch.bss_l2 = dest;
			if (dest == NULL) {
				pr_err("L2 SRAM allocation failed\n",
					mod->name);
				return -1;
			}

		} else
			continue;

		s->sh_flags &= ~SHF_ALLOC;
		s->sh_addr = (unsigned long)dest;
	}

	return 0;
}
示例#4
0
int
apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
		   unsigned int symindex, unsigned int relsec,
		   struct module *mod)
{
	unsigned int i;
	Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr;
	Elf32_Sym *sym;
	unsigned long location, value, size;

	pr_debug("applying relocate section %u to %u\n", mod->name,
		relsec, sechdrs[relsec].sh_info);

	for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
		/* This is where to make the change */
		location = sechdrs[sechdrs[relsec].sh_info].sh_addr +
		           rel[i].r_offset;

		/* This is the symbol it is referring to. Note that all
		   undefined symbols have been resolved. */
		sym = (Elf32_Sym *) sechdrs[symindex].sh_addr
		    + ELF32_R_SYM(rel[i].r_info);
		value = sym->st_value;
		value += rel[i].r_addend;

#ifdef CONFIG_SMP
		if (location >= COREB_L1_DATA_A_START) {
			pr_err("cannot relocate in L1: %u (SMP kernel)",
				mod->name, ELF32_R_TYPE(rel[i].r_info));
			return -ENOEXEC;
		}
#endif

		pr_debug("location is %lx, value is %lx type is %d\n",
			mod->name, location, value, ELF32_R_TYPE(rel[i].r_info));

		switch (ELF32_R_TYPE(rel[i].r_info)) {

		case R_BFIN_HUIMM16:
			value >>= 16;
		case R_BFIN_LUIMM16:
		case R_BFIN_RIMM16:
			size = 2;
			break;
		case R_BFIN_BYTE4_DATA:
			size = 4;
			break;

		case R_BFIN_PCREL24:
		case R_BFIN_PCREL24_JUMP_L:
		case R_BFIN_PCREL12_JUMP:
		case R_BFIN_PCREL12_JUMP_S:
		case R_BFIN_PCREL10:
			pr_err("unsupported relocation: %u (no -mlong-calls?)\n",
				mod->name, ELF32_R_TYPE(rel[i].r_info));
			return -ENOEXEC;

		default:
			pr_err("unknown relocation: %u\n", mod->name,
				ELF32_R_TYPE(rel[i].r_info));
			return -ENOEXEC;
		}

		switch (bfin_mem_access_type(location, size)) {
		case BFIN_MEM_ACCESS_CORE:
		case BFIN_MEM_ACCESS_CORE_ONLY:
			memcpy((void *)location, &value, size);
			break;
		case BFIN_MEM_ACCESS_DMA:
			dma_memcpy((void *)location, &value, size);
			break;
		case BFIN_MEM_ACCESS_ITEST:
			isram_memcpy((void *)location, &value, size);
			break;
		default:
			pr_err("invalid relocation for %#lx\n",
				mod->name, location);
			return -ENOEXEC;
		}
	}

	return 0;
}
示例#5
0
int main_simple(void)
{

    static uint32_t g_ui32SrcBuf[MEM_BUFFER_SIZE];
    static uint32_t g_ui32DstBuf[MEM_BUFFER_SIZE];

    /* Set up clock for 120MHz */
    MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
                            SYSCTL_OSC_MAIN |
                            SYSCTL_USE_PLL |
                            SYSCTL_CFG_VCO_480), 120000000);

    /* Set up SysTick timer */
    ROM_SysTickPeriodSet(0xffffffff);
    ROM_SysTickEnable();

    /* Enable interrupts */
    ROM_IntMasterEnable();

    init_dma_memcpy(UDMA_CHANNEL_SW);

    { /* Scope out the counter */
        uint_fast16_t ui16Idx;

        /* Fill source buffer with varying numbers */
        for(ui16Idx = 0; ui16Idx < MEM_BUFFER_SIZE; ui16Idx++)
        {
            g_ui32SrcBuf[ui16Idx] = ui16Idx;
        }
    }

    void *cbfn_ptr[2] = {&set_udma_txfer_done, NULL};

    volatile unsigned int t0 = (ROM_SysTickValueGet());

    dma_memcpy(
        g_ui32DstBuf,
        g_ui32SrcBuf,
        MEM_BUFFER_SIZE,
        UDMA_CHANNEL_SW,
        cbfn_ptr[0]
    );

    /* Wait for udma txfer to complete */
    while (!udma_txfer_done);

    volatile unsigned int t1 = (ROM_SysTickValueGet());

    memcpy(g_ui32DstBuf, g_ui32SrcBuf, MEM_BUFFER_SIZE);
    volatile unsigned int t2 = (ROM_SysTickValueGet());

    t2 = t1 - t2; /* Calc time taken for memcpy */
    t1 = t0 - t1; /* Calc time taken for dma_memcpy */

    volatile uint32_t count_past_dma = 0;

    /* Wait around compare txfer times */
    while (1){
        count_past_dma++;
    }

    return 0;

}
示例#6
0
int
module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
			  char *secstrings, struct module *mod)
{
	/*
                                                 
                                                    
                                                     
                                                     
                                                          
  */
	Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
	void *dest;

	for (s = sechdrs; s < sechdrs_end; ++s) {
		const char *shname = secstrings + s->sh_name;

		if (s->sh_size == 0)
			continue;

		if (!strcmp(".l1.text", shname) ||
		    (!strcmp(".text", shname) &&
		     (hdr->e_flags & EF_BFIN_CODE_IN_L1))) {

			dest = l1_inst_sram_alloc(s->sh_size);
			mod->arch.text_l1 = dest;
			if (dest == NULL) {
				pr_err("L1 inst memory allocation failed\n");
				return -1;
			}
			dma_memcpy(dest, (void *)s->sh_addr, s->sh_size);

		} else if (!strcmp(".l1.data", shname) ||
		           (!strcmp(".data", shname) &&
		            (hdr->e_flags & EF_BFIN_DATA_IN_L1))) {

			dest = l1_data_sram_alloc(s->sh_size);
			mod->arch.data_a_l1 = dest;
			if (dest == NULL) {
				pr_err("L1 data memory allocation failed\n");
				return -1;
			}
			memcpy(dest, (void *)s->sh_addr, s->sh_size);

		} else if (!strcmp(".l1.bss", shname) ||
		           (!strcmp(".bss", shname) &&
		            (hdr->e_flags & EF_BFIN_DATA_IN_L1))) {

			dest = l1_data_sram_zalloc(s->sh_size);
			mod->arch.bss_a_l1 = dest;
			if (dest == NULL) {
				pr_err("L1 data memory allocation failed\n");
				return -1;
			}

		} else if (!strcmp(".l1.data.B", shname)) {

			dest = l1_data_B_sram_alloc(s->sh_size);
			mod->arch.data_b_l1 = dest;
			if (dest == NULL) {
				pr_err("L1 data memory allocation failed\n");
				return -1;
			}
			memcpy(dest, (void *)s->sh_addr, s->sh_size);

		} else if (!strcmp(".l1.bss.B", shname)) {

			dest = l1_data_B_sram_alloc(s->sh_size);
			mod->arch.bss_b_l1 = dest;
			if (dest == NULL) {
				pr_err("L1 data memory allocation failed\n");
				return -1;
			}
			memset(dest, 0, s->sh_size);

		} else if (!strcmp(".l2.text", shname) ||
		           (!strcmp(".text", shname) &&
		            (hdr->e_flags & EF_BFIN_CODE_IN_L2))) {

			dest = l2_sram_alloc(s->sh_size);
			mod->arch.text_l2 = dest;
			if (dest == NULL) {
				pr_err("L2 SRAM allocation failed\n");
				return -1;
			}
			memcpy(dest, (void *)s->sh_addr, s->sh_size);

		} else if (!strcmp(".l2.data", shname) ||
		           (!strcmp(".data", shname) &&
		            (hdr->e_flags & EF_BFIN_DATA_IN_L2))) {

			dest = l2_sram_alloc(s->sh_size);
			mod->arch.data_l2 = dest;
			if (dest == NULL) {
				pr_err("L2 SRAM allocation failed\n");
				return -1;
			}
			memcpy(dest, (void *)s->sh_addr, s->sh_size);

		} else if (!strcmp(".l2.bss", shname) ||
		           (!strcmp(".bss", shname) &&
		            (hdr->e_flags & EF_BFIN_DATA_IN_L2))) {

			dest = l2_sram_zalloc(s->sh_size);
			mod->arch.bss_l2 = dest;
			if (dest == NULL) {
				pr_err("L2 SRAM allocation failed\n");
				return -1;
			}

		} else
			continue;

		s->sh_flags &= ~SHF_ALLOC;
		s->sh_addr = (unsigned long)dest;
	}

	return 0;
}