/** * If the PLL settings are in place switch the CPU core frequency to the max. value */ static int pcm038_power_init(void) { uint32_t spctl0; int ret; spctl0 = get_pll_spctl10(); /* PLL registers already set to their final values? */ if (spctl0 == SPCTL0_VAL && MPCTL0 == MPCTL0_VAL) { console_flush(); ret = pmic_power(); if (ret == 0) { /* wait for required power level to run the CPU at 400 MHz */ udelay(100000); CSCR = CSCR_VAL_FINAL; PCDR0 = 0x130410c3; PCDR1 = 0x09030911; /* Clocks have changed. Notify clients */ clock_notifier_call_chain(); } else { printf("Failed to initialize PMIC. Will continue with low CPU speed\n"); } } /* clock gating enable */ GPCR = 0x00050f08; return 0; }
/** * If the PLL settings are in place switch the CPU core frequency to the max. value */ static int pcm038_power_init(void) { uint32_t spctl0 = get_pll_spctl10(); struct mc13xxx *mc13xxx = mc13xxx_get(); /* PLL registers already set to their final values? */ if (spctl0 == SPCTL0_VAL && readl(MX27_CCM_BASE_ADDR + MX27_MPCTL0) == MPCTL0_VAL) { console_flush(); if (mc13xxx) { mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0), MC13783_SWX_VOLTAGE(MC13783_SWX_VOLTAGE_1_450) | MC13783_SWX_VOLTAGE_DVS(MC13783_SWX_VOLTAGE_1_450) | MC13783_SWX_VOLTAGE_STANDBY(MC13783_SWX_VOLTAGE_1_450)); mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(4), MC13783_SW1A_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) | MC13783_SW1A_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) | MC13783_SW1A_SOFTSTART | MC13783_SW1B_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) | MC13783_SW1B_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) | MC13783_SW1B_SOFTSTART | MC13783_SW_PLL_FACTOR(32)); /* Setup VMMC voltage */ if (IS_ENABLED(CONFIG_MCI_IMX)) { u32 val; mc13xxx_reg_read(mc13xxx, MC13783_REG_REG_SETTING(1), &val); /* VMMC1 = 3.00 V */ val &= ~(7 << 6); val |= 6 << 6; mc13xxx_reg_write(mc13xxx, MC13783_REG_REG_SETTING(1), val); mc13xxx_reg_read(mc13xxx, MC13783_REG_REG_MODE(1), &val); /* Enable VMMC1 */ val |= 1 << 18; mc13xxx_reg_write(mc13xxx, MC13783_REG_REG_MODE(1), val); } /* wait for required power level to run the CPU at 400 MHz */ udelay(100000); writel(CSCR_VAL_FINAL, MX27_CCM_BASE_ADDR + MX27_CSCR); writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0); writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1); /* Clocks have changed. Notify clients */ clock_notifier_call_chain(); } else { pr_err("Failed to initialize PMIC. Will continue with low CPU speed\n"); } } /* clock gating enable */ writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR); return 0; }