int mtk_wdt_boot_check(void) { unsigned int wdt_sta = mtk_wdt_check_status(); #if 0 if (wdt_sta == MTK_WDT_STATUS_HWWDT_RST) { /* For E1 bug, that SW reset value is 0xC000, we using "==" to check */ /* Time out reboot always by pass power key */ print ("TO reset, need bypass power key\n"); return WDT_BY_PASS_PWK_REBOOT; } else if (wdt_sta & MTK_WDT_STATUS_SWWDT_RST) { #endif /* * For DA download hope to timeout reboot, and boot to u-boot/kernel configurable reason, * we set both timeout reboot and software reboot can check whether bypass power key. */ if (wdt_sta & (MTK_WDT_STATUS_HWWDT_RST|MTK_WDT_STATUS_SWWDT_RST|MTK_WDT_STATUS_PCMWDT_RST|MTK_WDT_STATUS_SPMWDT_RST)) { if (rgu_mode & MTK_WDT_MODE_AUTO_RESTART) { /* HW/SW reboot, and auto restart is set, means bypass power key */ print ("SW RST with bypass power key\n"); return WDT_BY_PASS_PWK_REBOOT; } else { print ("SW RST without bypass power key\n"); return WDT_NORMAL_REBOOT; } } return WDT_NOT_WDT_REBOOT; } void mtk_wdt_init(void) { #if defined(CONFIG_EMULATION_EARLY_PORTING) print("==== Dump RGU Reg ========\n"); print("RGU MODE: %x\n", DRV_Reg32(MTK_WDT_MODE)); print("RGU LENGTH: %x\n", DRV_Reg32(MTK_WDT_LENGTH)); print("RGU STA: %x\n", DRV_Reg32(MTK_WDT_STATUS)); print("RGU INTERVAL: %x\n", DRV_Reg32(MTK_WDT_INTERVAL)); print("==== Dump RGU Reg End ====\n"); DRV_WriteReg32(0x10007000, 0x22000000); //mt6572 emulation #else unsigned wdt_sta; /* Dump RGU regisers */ print("==== Dump RGU Reg ========\n"); print("RGU MODE: %x\n", DRV_Reg32(MTK_WDT_MODE)); print("RGU EN_FAST: %x\n", DRV_Reg32(MTK_WDT_EN_FAST)); print("RGU LENGTH: %x\n", DRV_Reg32(MTK_WDT_LENGTH)); print("RGU STA: %x\n", DRV_Reg32(MTK_WDT_STATUS)); print("RGU DRAM_CTL: %x\n", DRV_Reg32(MTK_WDT_DRAMC_CTL)); print("RGU INTERVAL: %x\n", DRV_Reg32(MTK_WDT_INTERVAL)); print("RGU FAST_SWSYSRST: %x\n", DRV_Reg32(MTK_WDT_FAST_SWSYSRST)); print("==== Dump RGU Reg End ====\n"); rgu_mode = DRV_Reg32(MTK_WDT_MODE); wdt_sta = mtk_wdt_check_status(); // This function will store the reset reason: Time out/ SW trigger if (((wdt_sta & MTK_WDT_STATUS_HWWDT_RST) || (wdt_sta & MTK_WDT_STATUS_PCMWDT_RST)) && (rgu_mode&MTK_WDT_MODE_AUTO_RESTART)) { /* For E1 bug, that SW reset value is 0xC000, we using "==" to check */ /* Time out reboot always by pass power key */ g_rgu_status = RE_BOOT_BY_WDT_HW; } else if (wdt_sta & MTK_WDT_STATUS_SWWDT_RST) { g_rgu_status = RE_BOOT_BY_WDT_SW; } else { g_rgu_status = RE_BOOT_REASON_UNKNOW; } if(wdt_sta & MTK_WDT_STATUS_IRQWDT_RST) { g_rgu_status |= RE_BOOT_WITH_INTTERUPT; } if(wdt_sta & MTK_WDT_STATUS_SPMWDT_RST) { g_rgu_status |= RE_BOOT_WITH_THERMAL; } if(wdt_sta & MTK_WDT_STATUS_PCMWDT_RST) { g_rgu_status |= RE_BOOT_BY_SPM; } print ("g_rgu_satus:%d\n", g_rgu_status); mtk_wdt_mode_config(FALSE, FALSE, FALSE, FALSE, FALSE); // Wirte Mode register will clear status register mtk_wdt_check_trig_reboot_reason(); /* Setting timeout 10s */ mtk_wdt_set_time_out_value(16); #ifdef CFG_APWDT_DISABLE /* Config HW reboot mode */ mtk_wdt_mode_config(TRUE, FALSE, TRUE, FALSE, TRUE); mtk_wdt_restart(); #endif mtk_wdt_reset_deglitch_enable(); #endif }
int mtk_wdt_boot_check(void) { unsigned int wdt_sta = mtk_wdt_check_status(); #if 0 if (wdt_sta == MTK_WDT_STATUS_HWWDT_RST) { /* For E1 bug, that SW reset value is 0xC000, we using "==" to check */ /* Time out reboot always by pass power key */ print ("TO reset, need bypass power key\n"); return WDT_BY_PASS_PWK_REBOOT; } else if (wdt_sta & MTK_WDT_STATUS_SWWDT_RST) { #endif /* * For DA download hope to timeout reboot, and boot to u-boot/kernel configurable reason, * we set both timeout reboot and software reboot can check whether bypass power key. */ if (wdt_sta & (MTK_WDT_STATUS_HWWDT_RST|MTK_WDT_STATUS_SWWDT_RST| MTK_WDT_STATUS_SPM_THERMAL_RST|MTK_WDT_STATUS_SPMWDT_RST| MTK_WDT_STATUS_THERMAL_DIRECT_RST|MTK_WDT_STATUS_SECURITY_RST |MTK_WDT_STATUS_DEBUGWDT_RST)) { if (rgu_mode & MTK_WDT_MODE_AUTO_RESTART) { /* HW/SW reboot, and auto restart is set, means bypass power key */ print ("SW reset with bypass power key flag\n"); return WDT_BY_PASS_PWK_REBOOT; } else { print ("SW reset without bypass power key flag\n"); return WDT_NORMAL_REBOOT; } } return WDT_NOT_WDT_REBOOT; } void mtk_wdt_init(void) { unsigned wdt_sta; unsigned int wdt_dbg_ctrl; unsigned int nonrst; /* Dump RGU regisers */ print("==== Dump RGU Reg ========\n"); print("RGU MODE: %x\n", DRV_Reg32(MTK_WDT_MODE)); print("RGU LENGTH: %x\n", DRV_Reg32(MTK_WDT_LENGTH)); print("RGU STA: %x\n", DRV_Reg32(MTK_WDT_STATUS)); print("RGU INTERVAL: %x\n", DRV_Reg32(MTK_WDT_INTERVAL)); print("RGU SWSYSRST: %x\n", DRV_Reg32(MTK_WDT_SWSYSRST)); print("==== Dump RGU Reg End ====\n"); rgu_mode = DRV_Reg32(MTK_WDT_MODE); wdt_sta = mtk_wdt_check_status(); // This function will store the reset reason: Time out/ SW trigger if ((wdt_sta & MTK_WDT_STATUS_HWWDT_RST)&&(rgu_mode&MTK_WDT_MODE_AUTO_RESTART)) { /* For E1 bug, that SW reset value is 0xC000, we using "==" to check */ /* Time out reboot always by pass power key */ g_rgu_status = RE_BOOT_BY_WDT_HW; } else if (wdt_sta & MTK_WDT_STATUS_SWWDT_RST) { g_rgu_status = RE_BOOT_BY_WDT_SW; } else { g_rgu_status = RE_BOOT_REASON_UNKNOW; } if(wdt_sta & MTK_WDT_STATUS_IRQWDT_RST) { g_rgu_status |= RE_BOOT_WITH_INTTERUPT; } if(wdt_sta & MTK_WDT_STATUS_SPM_THERMAL_RST) { g_rgu_status |= RE_BOOT_BY_SPM_THERMAL; } if(wdt_sta & MTK_WDT_STATUS_SPMWDT_RST) { g_rgu_status |= RE_BOOT_BY_SPM; } if(wdt_sta & MTK_WDT_STATUS_THERMAL_DIRECT_RST) { g_rgu_status |= RE_BOOT_BY_THERMAL_DIRECT; } if(wdt_sta & MTK_WDT_STATUS_DEBUGWDT_RST) { g_rgu_status |= RE_BOOT_BY_DEBUG; } if(wdt_sta & MTK_WDT_STATUS_SECURITY_RST) { g_rgu_status |= RE_BOOT_BY_SECURITY; } print ("RGU: g_rgu_satus:%d\n", g_rgu_status); mtk_wdt_mode_config(FALSE, FALSE, FALSE, FALSE, FALSE); // Wirte Mode register will clear status register mtk_wdt_check_trig_reboot_reason(); /* Setting timeout 10s */ mtk_wdt_set_time_out_value(16); #if (!CFG_APWDT_DISABLE) /* Config HW reboot mode */ mtk_wdt_mode_config(TRUE, TRUE, TRUE, FALSE, TRUE); mtk_wdt_restart(); #endif /* * E3 ECO * reset will delay 2ms after set SW_WDT in register */ nonrst = READ_REG(MTK_WDT_NONRST_REG); nonrst = (nonrst | (1<<29)); WRITE_REG(nonrst, MTK_WDT_NONRST_REG); print("WDT NONRST=0x%x\n", READ_REG(MTK_WDT_NONRST_REG)); // set mcu_lath_en requir by pl owner confirmed by RGU DE /*SW workaround close DEBUG IRQ for C2K*/ nonrst = READ_REG(MTK_WDT_REQ_IRQ_EN); nonrst &= (~(1<<19)); nonrst |= MTK_WDT_REQ_IRQ_KEY; WRITE_REG(nonrst, MTK_WDT_REQ_IRQ_EN); /*disable spm_thermal bit, becaue spm_thermal had been remove from HW*/ nonrst = READ_REG(MTK_WDT_REQ_IRQ_EN); nonrst &= (~(1<<0)); /*disale spm_thermal irq*/ nonrst |= MTK_WDT_REQ_IRQ_KEY; WRITE_REG(nonrst, MTK_WDT_REQ_IRQ_EN); print("WDT IRQ_EN=0x%x\n", READ_REG(MTK_WDT_REQ_IRQ_EN)); nonrst = READ_REG(MTK_WDT_REQ_MODE); nonrst &= (~(1<<0)); /*disale spm_thermal reset*/ nonrst |= 0x33000000; WRITE_REG(nonrst, MTK_WDT_REQ_MODE); print("WDT REQ_EN=0x%x\n", READ_REG(MTK_WDT_REQ_MODE)); wdt_dbg_ctrl = READ_REG(MTK_WDT_DEBUG_CTL); wdt_dbg_ctrl |= MTK_RG_MCU_LATH_EN; wdt_dbg_ctrl |= MTK_DEBUG_CTL_KEY; WRITE_REG(wdt_dbg_ctrl, MTK_WDT_DEBUG_CTL); print("RGU %s:MTK_WDT_DEBUG_CTL(%x)\n", __func__,wdt_dbg_ctrl); }