int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue) //do not know what to do with pValue { if(InterruptHdl == NULL) { //De-register Interprocessor communication interrupt between App and NWP #ifdef SL_PLATFORM_MULTI_THREADED osi_InterruptDeRegister(INT_NWPIC); #else IntDisable(INT_NWPIC); IntUnregister(INT_NWPIC); IntPendClear(INT_NWPIC); #endif g_pHostIntHdl = NULL; } else { g_pHostIntHdl = InterruptHdl; #if 0 //Setting the 14th and 13th bit to '01' to make the HOST_IRQ edge triggered HWREG(0x4402E168) |= 0x2000; #endif #ifdef SL_PLATFORM_MULTI_THREADED IntPendClear(INT_NWPIC); osi_InterruptRegister(INT_NWPIC, (P_OSI_INTR_ENTRY)HostIntHanlder,INT_PRIORITY_LVL_1); #else IntRegister(INT_NWPIC, HostIntHanlder); IntPrioritySet(INT_NWPIC, INT_PRIORITY_LVL_1); IntPendClear(INT_NWPIC); IntEnable(INT_NWPIC); #endif } return 0; }
int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue) //do not know what to do with pValue { if(InterruptHdl == NULL) { //De-register Interprocessor communication interrupt between App and NWP #ifdef SL_PLATFORM_MULTI_THREADED osi_InterruptDeRegister(INT_NWPIC); #else MAP_IntDisable(INT_NWPIC); MAP_IntUnregister(INT_NWPIC); MAP_IntPendClear(INT_NWPIC); #endif } else { #ifdef SL_PLATFORM_MULTI_THREADED MAP_IntPendClear(INT_NWPIC); osi_InterruptRegister(INT_NWPIC, (P_OSI_INTR_ENTRY)InterruptHdl, INT_PRIORITY_LVL_1); #else MAP_IntRegister(INT_NWPIC, InterruptHdl); MAP_IntPrioritySet(INT_NWPIC, INT_PRIORITY_LVL_1); MAP_IntPendClear(INT_NWPIC); MAP_IntEnable(INT_NWPIC); #endif } return 0; }
/*! \brief closes an opened spi communication port \param fd - file descriptor of an opened SPI channel \return upon successful completion, the function shall return 0. Otherwise, -1 shall be returned \sa spi_Open \note \warning */ int spi_Close(Fd_t fd) { unsigned long ulBase = LSPI_BASE; g_SpiFd = 0; if(g_ucDMAEnabled) { //Simplelink_UDMADeInit(); #ifdef SL_PLATFORM_MULTI_THREADED osi_InterruptDeRegister(INT_LSPI); osi_MsgQDelete(&DMAMsgQ); #else SPIIntUnregister(ulBase); g_cDummy = 0; #endif SPIFIFODisable(ulBase,SPI_RX_FIFO); SPIFIFODisable(ulBase,SPI_TX_FIFO); SPIDmaDisable(ulBase,SPI_RX_DMA); SPIDmaDisable(ulBase,SPI_TX_DMA); } //Disable Chip Select SPICSDisable(LSPI_BASE); //Disable SPI Channel SPIDisable(ulBase); // Reset SPI SPIReset(ulBase); // Enable SPI Peripheral PRCMPeripheralClkDisable(PRCM_LSPI,PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK); return 0; }