void osl_pci_write_config(osl_t *osh, unsigned int offset, unsigned int size, unsigned int val) { uint retry = PCI_CFG_RETRY; /* PR15065: faulty cardbus controller bug */ pciinfo_t *pciinfo = (pciinfo_t *)(osh->devinfo); ASSERT(size == 4); do { pciConfigOutLong(pciinfo->bus, pciinfo->dev, pciinfo->func, offset, val); /* PR15065: PCI_BAR0_WIN is believed to be the only pci cfg write that can occur * when dma activity is possible */ if (offset != PCI_BAR0_WIN) break; if (osl_pci_read_config(osh, offset, size) == val) break; } while (retry--); #ifdef BCMDBG if (retry < PCI_CFG_RETRY) printf("PCI CONFIG WRITE access to %d required %d retries\n", offset, (PCI_CFG_RETRY - retry)); #endif /* BCMDBG */ }
void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val) { uint retry = PCI_CFG_RETRY; ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC))); ASSERT(size == 4); do { pci_write_config_dword(osh->pdev, offset, val); if (offset != PCI_BAR0_WIN) break; if (osl_pci_read_config(osh, offset, size) == val) break; } while (retry--); }
void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val) { uint retry = PCI_CFG_RETRY; ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC))); ASSERT(size == 4); do { pci_write_config_dword(osh->pdev, offset, val); if (offset != PCI_BAR0_WIN) break; if (osl_pci_read_config(osh, offset, size) == val) break; } while (retry--); #ifdef BCMDBG if (retry < PCI_CFG_RETRY) printk("PCI CONFIG WRITE access to %d required %d retries\n", offset, (PCI_CFG_RETRY - retry)); #endif }