static int ali_configure(void) { u32 temp; struct aper_size_info_32 *current_size; current_size = A_SIZE_32(agp_bridge->current_size); /* aperture size and gatt addr */ pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp); temp = (((temp & 0x00000ff0) | (agp_bridge->gatt_bus_addr & 0xfffff000)) | (current_size->size_value & 0xf)); pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE, temp); /* tlb control */ pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp); pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010)); /* address to map to */ agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR); #if 0 if (agp_bridge->type == ALI_M1541) { u32 nlvm_addr = 0; switch (current_size->size_value) { case 0: break; case 1: nlvm_addr = 0x100000;break; case 2: nlvm_addr = 0x200000;break; case 3: nlvm_addr = 0x400000;break; case 4: nlvm_addr = 0x800000;break; case 6: nlvm_addr = 0x1000000;break; case 7: nlvm_addr = 0x2000000;break; case 8: nlvm_addr = 0x4000000;break; case 9: nlvm_addr = 0x8000000;break; case 10: nlvm_addr = 0x10000000;break; default: break; } nlvm_addr--; nlvm_addr&=0xfff00000; nlvm_addr+= agp_bridge->gart_bus_addr; nlvm_addr|=(agp_bridge->gart_bus_addr>>12); dev_info(&agp_bridge->dev->dev, "nlvm top &base = %8x\n", nlvm_addr); }
static int via_configure(void) { struct aper_size_info_8 *current_size; current_size = A_SIZE_8(agp_bridge->current_size); /* aperture size */ pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, current_size->size_value); /* address to map to */ agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR); /* GART control register */ pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f); /* attbase - aperture GATT base */ pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE, (agp_bridge->gatt_bus_addr & 0xfffff000) | 3); return 0; }
static int via_configure_agp3(void) { u32 temp; struct aper_size_info_16 *current_size; current_size = A_SIZE_16(agp_bridge->current_size); /* address to map to */ agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR); /* attbase - aperture GATT base */ pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE, agp_bridge->gatt_bus_addr & 0xfffff000); /* 1. Enable GTLB in RX90<7>, all AGP aperture access needs to fetch * translation table first. * 2. Enable AGP aperture in RX91<0>. This bit controls the enabling of the * graphics AGP aperture for the AGP3.0 port. */ pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp); pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp | (3<<7)); return 0; }
static int ati_create_gatt_table(struct agp_bridge_data *bridge) { struct aper_size_info_lvl2 *value; struct ati_page_map page_dir; unsigned long __iomem *cur_gatt; unsigned long addr; int retval; u32 temp; int i; struct aper_size_info_lvl2 *current_size; value = A_SIZE_LVL2(agp_bridge->current_size); retval = ati_create_page_map(&page_dir); if (retval != 0) return retval; retval = ati_create_gatt_pages(value->num_entries / 1024); if (retval != 0) { ati_free_page_map(&page_dir); return retval; } agp_bridge->gatt_table_real = (u32 *)page_dir.real; agp_bridge->gatt_table = (u32 __iomem *) page_dir.remapped; agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real); /* Write out the size register */ current_size = A_SIZE_LVL2(agp_bridge->current_size); if (is_r200()) { pci_read_config_dword(agp_bridge->dev, ATI_RS100_APSIZE, &temp); temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 0x00000001); pci_write_config_dword(agp_bridge->dev, ATI_RS100_APSIZE, temp); pci_read_config_dword(agp_bridge->dev, ATI_RS100_APSIZE, &temp); } else { pci_read_config_dword(agp_bridge->dev, ATI_RS300_APSIZE, &temp); temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 0x00000001); pci_write_config_dword(agp_bridge->dev, ATI_RS300_APSIZE, temp); pci_read_config_dword(agp_bridge->dev, ATI_RS300_APSIZE, &temp); } /* * Get the address for the gart region. * This is a bus address even on the alpha, b/c its * used to program the agp master not the cpu */ addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR); agp_bridge->gart_bus_addr = addr; /* Calculate the agp offset */ for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) { writel(virt_to_phys(ati_generic_private.gatt_pages[i]->real) | 1, page_dir.remapped+GET_PAGE_DIR_OFF(addr)); readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr)); /* PCI Posting. */ } for (i = 0; i < value->num_entries; i++) { addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr; cur_gatt = GET_GATT(addr); writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr)); } return 0; }