void spi_master_close(const spi_master_hw_instance_t spi_master_hw_instance)
{
#if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE)
volatile spi_master_instance_t * p_spi_instance = spi_master_get_instance(
spi_master_hw_instance);
APP_ERROR_CHECK_BOOL(p_spi_instance != NULL);
/* Disable interrupt */
APP_ERROR_CHECK(sd_nvic_ClearPendingIRQ(p_spi_instance->irq_type));
APP_ERROR_CHECK(sd_nvic_DisableIRQ(p_spi_instance->irq_type));
p_spi_instance->p_nrf_spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
/* Set Slave Select pin as input with pull-up. */
nrf_gpio_pin_set(p_spi_instance->pin_slave_select);
nrf_gpio_cfg_input(p_spi_instance->pin_slave_select, NRF_GPIO_PIN_PULLUP);
p_spi_instance->pin_slave_select = (uint8_t)0xFF;
/* Disconnect pins from SPI hardware */
p_spi_instance->p_nrf_spi->PSELSCK = (uint32_t)SPI_PIN_DISCONNECTED;
p_spi_instance->p_nrf_spi->PSELMOSI = (uint32_t)SPI_PIN_DISCONNECTED;
p_spi_instance->p_nrf_spi->PSELMISO = (uint32_t)SPI_PIN_DISCONNECTED;
/* Reset to default values */
spi_master_init_hw_instance(NULL, (IRQn_Type)0, p_spi_instance, false);
#else
return;
#endif
}
void softdevice_handler_suspend()
{
#ifdef SOFTDEVICE_PRESENT
ret_code_t err_code = sd_nvic_DisableIRQ((IRQn_Type)SOFTDEVICE_EVT_IRQ);
APP_ERROR_CHECK(err_code);
#else
NVIC_DisableIRQ(SOFTDEVICE_EVT_IRQ);
#endif
m_suspended = true;
return;
}
static uint16_t
adc_read_blocking()
{
while (NRF_ADC->BUSY == 1) {
// __asm("nop");
}
NRF_ADC->EVENTS_END = 0;
sd_nvic_DisableIRQ(ADC_IRQn);
NRF_ADC->INTENCLR = ADC_INTENCLR_END_Enabled;
NRF_ADC->TASKS_START = 1;
adc_config();
NRF_ADC->ENABLE = ADC_ENABLE_ENABLE_Enabled;
while (NRF_ADC->EVENTS_END == 0) {
// __asm("nop");
}
uint16_t batt_lvl_in_milli_volts;
uint16_t result = NRF_ADC->RESULT;
batt_lvl_in_milli_volts = ADC_RESULT_IN_MILLI_VOLTS(result);
result = battery_level_in_percent(batt_lvl_in_milli_volts);
NRF_ADC->EVENTS_END = 0;
NRF_ADC->TASKS_STOP = 1;
return result;
}
uint32_t spi_master_send_recv(const spi_master_hw_instance_t spi_master_hw_instance,
uint8_t * const p_tx_buf, const uint16_t tx_buf_len,
uint8_t * const p_rx_buf, const uint16_t rx_buf_len)
{
#if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE)
volatile spi_master_instance_t * p_spi_instance = spi_master_get_instance(
spi_master_hw_instance);
APP_ERROR_CHECK_BOOL(p_spi_instance != NULL);
uint32_t err_code = NRF_SUCCESS;
uint16_t max_length = 0;
uint8_t nested_critical_region = 0;
//Check if disable all IRQs flag is set
if (p_spi_instance->disable_all_irq)
{
//Disable interrupts.
APP_ERROR_CHECK(sd_nvic_critical_region_enter(&nested_critical_region));
}
else
{
//Disable interrupt SPI.
APP_ERROR_CHECK(sd_nvic_DisableIRQ(p_spi_instance->irq_type));
}
//Initialize and perform data transfer
if (p_spi_instance->state == SPI_MASTER_STATE_IDLE)
{
max_length = (rx_buf_len > tx_buf_len) ? rx_buf_len : tx_buf_len;
if (max_length > 0)
{
p_spi_instance->state = SPI_MASTER_STATE_BUSY;
p_spi_instance->bytes_count = 0;
p_spi_instance->started_flag = false;
p_spi_instance->max_length = max_length;
/* Initialize buffers */
spi_master_buffer_init(p_tx_buf,
tx_buf_len,
&(p_spi_instance->p_tx_buffer),
&(p_spi_instance->tx_length),
&(p_spi_instance->tx_index));
spi_master_buffer_init(p_rx_buf,
rx_buf_len,
&(p_spi_instance->p_rx_buffer),
&(p_spi_instance->rx_length),
&(p_spi_instance->rx_index));
nrf_gpio_pin_clear(p_spi_instance->pin_slave_select);
spi_master_send_initial_bytes(p_spi_instance);
}
else
{
err_code = NRF_ERROR_INVALID_PARAM;
}
}
else
{
err_code = NRF_ERROR_BUSY;
}
//Check if disable all IRQs flag is set.
if (p_spi_instance->disable_all_irq)
{
//Enable interrupts.
APP_ERROR_CHECK(sd_nvic_critical_region_exit(nested_critical_region));
}
else
{
//Enable SPI interrupt.
APP_ERROR_CHECK(sd_nvic_EnableIRQ(p_spi_instance->irq_type));
}
return err_code;
#else
return NRF_ERROR_NOT_SUPPORTED;
#endif
}
