void init_tlbs(void) { int i; for (i = 0; i < num_tlb_entries; i++) { set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn, tlb_table[i].perms, tlb_table[i].wimge, tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize, tlb_table[i].iprot); } return ; }
int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited * so that flash can be erased properly. */ /* Flush d-cache and invalidate i-cache of any FLASH data */ flush_dcache(); invalidate_icache(); if (flash_esel == -1) { /* very unlikely unless something is messed up */ puts("Error: Could not find TLB for FLASH BASE\n"); flash_esel = 2; /* give our best effort to continue */ } else { /* invalidate existing TLB entry for flash + promjet */ disable_tlb(flash_esel); } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* Disable remote I2C connection to qixis fpga */ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); /* * Adjust core voltage according to voltage ID * This function changes I2C mux to channel 2. */ if (adjust_vdd(0)) printf("Warning: Adjusting core voltage failed.\n"); brd_mux_lane_to_slot(); select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); return 0; }
int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash region to caching-inhibited * so that flash can be erased properly. */ /* Flush d-cache and invalidate i-cache of any FLASH data */ flush_dcache(); invalidate_icache(); /* invalidate existing TLB entry for flash */ disable_tlb(flash_esel); set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_16M, 1); return 0; }
int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited * so that flash can be erased properly. */ /* Flush d-cache and invalidate i-cache of any FLASH data */ flush_dcache(); invalidate_icache(); /* invalidate existing TLB entry for flash + promjet */ disable_tlb(flash_esel); set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ return 0; }
int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_NAND_BASE; const u8 flash_esel = 0; /* * Remap Boot flash to caching-inhibited * so that flash can be erased properly. */ /* Flush d-cache and invalidate i-cache of any FLASH data */ flush_dcache(); invalidate_icache(); /* invalidate existing TLB entry for flash */ disable_tlb(flash_esel); set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 0, flash_esel, /* ts, esel */ BOOKE_PAGESZ_64M, 1); /* tsize, iprot */ return 0; }
unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { unsigned int tlb_size; unsigned int ram_tlb_index; unsigned int ram_tlb_address; /* * Determine size of each TLB1 entry. */ switch (memsize_in_meg) { case 16: case 32: tlb_size = BOOKE_PAGESZ_16M; break; case 64: case 128: tlb_size = BOOKE_PAGESZ_64M; break; case 256: case 512: tlb_size = BOOKE_PAGESZ_256M; break; case 1024: case 2048: if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx)) tlb_size = BOOKE_PAGESZ_1G; else tlb_size = BOOKE_PAGESZ_256M; break; default: puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G" " and 2G are supported.\n"); /* * The memory was not able to be mapped. * Default to a small size. */ tlb_size = BOOKE_PAGESZ_64M; memsize_in_meg = 64; break; } /* * Configure DDR TLB1 entries. * Starting at TLB1 8, use no more than 8 TLB1 entries. */ ram_tlb_index = 8; ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; while (ram_tlb_address < (memsize_in_meg * 1024 * 1024) && ram_tlb_index < 16) { set_tlb(1, ram_tlb_address, ram_tlb_address, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, ram_tlb_index, tlb_size, 1); ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); ram_tlb_index++; } /* * Confirm that the requested amount of memory was mapped. */ return memsize_in_meg; }