static int attribute_cntl_a_sequences(void) { BUFFER *bp = curbp; LINE *pastline; C_NUM offset; /* offset in cur line of place to attribute */ int count; #if EFFICIENCY_HACK AREGION *orig_attribs = bp->b_attribs; AREGION *new_attribs; #endif if ((pastline = setup_region()) == 0) return FALSE; while (DOT.l != pastline) { if (interrupted()) return FALSE; while (DOT.o < llength(DOT.l)) { if (CharAtDot() == CONTROL_A) { offset = decode_attribute(lvalue(DOT.l), (size_t) llength(DOT.l), (size_t) DOT.o, &count); if (offset > DOT.o) { #if EFFICIENCY_HACK new_attribs = bp->b_attribs; bp->b_attribs = orig_attribs; ldel_bytes((B_COUNT) (offset - DOT.o), FALSE); bp->b_attribs = new_attribs; #else ldel_bytes((B_COUNT) (offset - DOT.o), FALSE); #endif } set_mark_after(count, len_record_sep(bp)); if (apply_attribute()) (void) attributeregion(); } else { DOT.o += BytesAt(DOT.l, DOT.o); } } DOT.l = lforw(DOT.l); DOT.o = 0; } return TRUE; }
void execute(expr_list * ee) { int verbose = isatty(2); expr_list *l; int count, n; setup_region(); exprs = ee; G_add_error_handler(error_handler, NULL); for (l = ee; l; l = l->next) { expression *e = l->exp; const char *var; if (e->type != expr_type_binding && e->type != expr_type_function) G_fatal_error("internal error: execute: invalid type: %d", e->type); if (e->type != expr_type_binding) continue; var = e->data.bind.var; if (!overwrite_flag && check_output_map(var)) G_fatal_error(_("output map <%s> exists. To overwrite, use the --overwrite flag"), var); } for (l = ee; l; l = l->next) { expression *e = l->exp; const char *var; expression *val; initialize(e); if (e->type != expr_type_binding) continue; var = e->data.bind.var; val = e->data.bind.val; e->data.bind.fd = open_output_map(var, val->res_type); } setup_maps(); count = rows * depths; n = 0; G_init_workers(); for (current_depth = 0; current_depth < depths; current_depth++) for (current_row = 0; current_row < rows; current_row++) { if (verbose) G_percent(n, count, 2); for (l = ee; l; l = l->next) { expression *e = l->exp; int fd; evaluate(e); if (e->type != expr_type_binding) continue; fd = e->data.bind.fd; put_map_row(fd, e->buf, e->res_type); } n++; } G_finish_workers(); if (verbose) G_percent(n, count, 2); for (l = ee; l; l = l->next) { expression *e = l->exp; const char *var; expression *val; int fd; if (e->type != expr_type_binding) continue; var = e->data.bind.var; val = e->data.bind.val; fd = e->data.bind.fd; close_output_map(fd); e->data.bind.fd = -1; if (val->type == expr_type_map) { if (val->data.map.mod == 'M') { copy_cats(var, val->data.map.idx); copy_colors(var, val->data.map.idx); } copy_history(var, val->data.map.idx); } else create_history(var, val); } G_unset_error_routine(); }
static int attribute_from_filter(void) { BUFFER *bp = curbp; LINE *pastline; int skip; size_t nbytes; size_t n; int done; int result = TRUE; int drained = FALSE; TRACE((T_CALLED "attribute_from_filter\n")); if ((pastline = setup_region()) == 0) { result = FALSE; #ifdef MDHILITE } else if (!b_val(bp, MDHILITE)) { discard_syntax_highlighting(); #endif } else if (open_region_filter() == TRUE) { discard_syntax_highlighting(); while (DOT.l != pastline) { if (interrupted()) { result = FALSE; break; } if (ffgetline(&nbytes) > FIOSUC) { drained = TRUE; break; } DOT.o = 0; for (n = 0; n < nbytes; n++) { if (fflinebuf[n] == CONTROL_A) { done = decode_attribute(fflinebuf, nbytes, n, &skip); if (done) { n = (size_t) (done - 1); set_mark_after(skip, 1); if (apply_attribute()) (void) attributeregion(); } } else { DOT.o += BytesAt(DOT.l, DOT.o); } } DOT.l = lforw(DOT.l); } /* some pipes will hang if they're not drained */ if (!drained) { while (ffgetline(&nbytes) <= FIOSUC) { ; } } (void) ffclose(); /* Ignore errors. */ attach_attrib(selbufp, &selregion); attach_attrib(startbufp, &startregion); #if OPT_HILITEMATCH if (bp->b_highlight & HILITE_ON) { bp->b_highlight |= HILITE_DIRTY; attrib_matches(); } #endif } returnCode(result); }
/** * Init Queue Manager SUbSystem (QMSS) * - Configure QMSS Driver * - Define Memory regions * - */ void init_qmss(int useMsmc){ int i, result; Qmss_InitCfg qmss_initCfg; Cppi_CpDmaInitCfg cpdmaCfg; Qmss_GlobalConfigParams qmss_globalCfg; /* Descriptor base addresses */ void* data_desc_base = (void*)align((int)msmc_mem_base); void* ctrl_desc_base = (void*)align((int)data_desc_base + DATA_DESC_NUM*DATA_DESC_SIZE); void* trace_desc_base = (void*)align((int)ctrl_desc_base + CTRL_DESC_NUM*CTRL_DESC_SIZE); void* fftc_desc_base = (void*)align((int)trace_desc_base + TRACE_DESC_NUM*TRACE_DESC_SIZE); if(useMsmc){ data_mem_base = align((int)fftc_desc_base + FFTC_DESC_NUM*FFTC_DESC_SIZE); }else{ data_mem_base = align((int)ddr_mem_base); } /* Initialize QMSS Driver */ memset (&qmss_initCfg, 0, sizeof (Qmss_InitCfg)); /* Use internal linking RAM */ qmss_initCfg.linkingRAM0Base = 0; qmss_initCfg.linkingRAM0Size = 0; qmss_initCfg.linkingRAM1Base = 0; qmss_initCfg.maxDescNum = DATA_DESC_NUM + CTRL_DESC_NUM + TRACE_DESC_NUM + FFTC_DESC_NUM; qmss_initCfg.pdspFirmware[0].pdspId = Qmss_PdspId_PDSP1; qmss_initCfg.pdspFirmware[0].firmware = &acc48_le; qmss_initCfg.pdspFirmware[0].size = sizeof (acc48_le); /* Bypass hardware initialization as it is done within Kernel */ qmss_initCfg.qmssHwStatus = QMSS_HW_INIT_COMPLETE; qmss_globalCfg = qmssGblCfgParams; /* Convert address to Virtual address */ for(i=0;i < (int)qmss_globalCfg.maxQueMgrGroups;i++){ TranslateAddress(qmss_globalCfg.groupRegs[i].qmConfigReg, qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_Qm_configRegs*); TranslateAddress(qmss_globalCfg.groupRegs[i].qmDescReg, qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_Qm_descriptor_region_configRegs*); TranslateAddress(qmss_globalCfg.groupRegs[i].qmQueMgmtReg, qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_Qm_queue_managementRegs*); TranslateAddress(qmss_globalCfg.groupRegs[i].qmQueMgmtProxyReg, qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_Qm_queue_managementRegs*); TranslateAddress(qmss_globalCfg.groupRegs[i].qmQueStatReg, qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_Qm_queue_status_configRegs*); TranslateAddress(qmss_globalCfg.groupRegs[i].qmStatusRAM, qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_Qm_Queue_Status*); TranslateAddress(qmss_globalCfg.groupRegs[i].qmQueMgmtDataReg, qmss_cfg_regs-CSL_QMSS_DATA_BASE, CSL_Qm_queue_managementRegs*); /* not supported on k2 hardware, and not used by lld */ qmss_globalCfg.groupRegs[i].qmQueMgmtProxyDataReg = 0; } for(i=0;i < QMSS_MAX_INTD;i++) TranslateAddress(qmss_globalCfg.regs.qmQueIntdReg[i], qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_Qm_intdRegs*); for(i=0;i < QMSS_MAX_PDSP;i++){ TranslateAddress(qmss_globalCfg.regs.qmPdspCmdReg[i], qmss_cfg_regs-CSL_QMSS_CFG_BASE, volatile uint32_t*); TranslateAddress(qmss_globalCfg.regs.qmPdspCtrlReg[i], qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_PdspRegs*); TranslateAddress(qmss_globalCfg.regs.qmPdspIRamReg[i], qmss_cfg_regs-CSL_QMSS_CFG_BASE, volatile uint32_t*); } TranslateAddress(qmss_globalCfg.regs.qmLinkingRAMReg, qmss_cfg_regs-CSL_QMSS_CFG_BASE, volatile uint32_t*); TranslateAddress(qmss_globalCfg.regs.qmBaseAddr, qmss_cfg_regs-CSL_QMSS_CFG_BASE, void*); if ((result = Qmss_init (&qmss_initCfg, &qmss_globalCfg)) != QMSS_SOK){ printf ("initQmss: Error initializing Queue Manager SubSystem, Error code : %d\n", result); abort(); } if ((result = Qmss_start ()) != QMSS_SOK){ printf ("initQmss: Error starting Queue Manager SubSystem, Error code : %d\n", result); abort(); } Cppi_GlobalCPDMAConfigParams translatedCppiGblCpdmaCfgParams[Cppi_CpDma_LAST+1]; Cppi_GlobalConfigParams translatedCppiGblCfgParams = cppiGblCfgParams; translatedCppiGblCfgParams.cpDmaCfgs = translatedCppiGblCpdmaCfgParams; #define translateCpdma(reg, type) (translatedCppiGblCfgParams.reg = (type)(((int) cppiGblCfgParams.reg ) + cppi_regs - CPPI_BASE_REG)) Cppi_CpDma cpdma; for(cpdma = Cppi_CpDma_SRIO_CPDMA; cpdma <= Cppi_CpDma_LAST; cpdma++){ translatedCppiGblCfgParams.cpDmaCfgs[cpdma] = cppiGblCfgParams.cpDmaCfgs[cpdma]; translateCpdma(cpDmaCfgs[cpdma].gblCfgRegs, CSL_Cppidma_global_configRegs*); translateCpdma(cpDmaCfgs[cpdma].txChRegs, CSL_Cppidma_tx_channel_configRegs*); translateCpdma(cpDmaCfgs[cpdma].rxChRegs, CSL_Cppidma_rx_channel_configRegs*); translateCpdma(cpDmaCfgs[cpdma].txSchedRegs,CSL_Cppidma_tx_scheduler_configRegs*); translateCpdma(cpDmaCfgs[cpdma].rxFlowRegs, CSL_Cppidma_rx_flow_configRegs*); } if ((result = Cppi_init (&translatedCppiGblCfgParams)) != CPPI_SOK){ printf ("Error initializing CPPI LLD, Error code : %d\n", result); abort(); } /* Setup memory regions */ /* Setup DATA region */ result = setup_region( data_desc_base, DATA_DESC_SIZE, DATA_DESC_NUM, 0, DATA_REG_NUM); if (result) abort(); /* Setup CTRL region */ result = setup_region( ctrl_desc_base, CTRL_DESC_SIZE, CTRL_DESC_NUM, DATA_DESC_NUM, CTRL_REG_NUM); if (result) abort(); /* Setup TRACE region */ result = setup_region( trace_desc_base, TRACE_DESC_SIZE, TRACE_DESC_NUM, DATA_DESC_NUM+CTRL_DESC_NUM, TRACE_REG_NUM); if (result) abort(); /* Setup FFTC region */ result = setup_region( fftc_desc_base, FFTC_DESC_SIZE, FFTC_DESC_NUM, DATA_DESC_NUM+CTRL_DESC_NUM+TRACE_DESC_NUM, FFTC_REG_NUM); if (result) abort(); /* Setup the driver for this FFTC peripheral instance number. */ /* Set up the FFTC CPDMA configuration */ memset (&cpdmaCfg, 0, sizeof (Cppi_CpDmaInitCfg)); cpdmaCfg.dmaNum = Cppi_CpDma_FFTC_A_CPDMA; /* Initialize FFTC CPDMA */ if ((hCppi[0] = Cppi_open (&cpdmaCfg)) == NULL){ printf ("Error initializing CPPI for FFTC CPDMA %d\n", cpdmaCfg.dmaNum); abort(); } /* Disable FFTC CDMA loopback */ if (Cppi_setCpdmaLoopback (hCppi[0], 0) != CPPI_SOK){ printf ("Error disabling loopback for FFTC CPDMA %d\n", cpdmaCfg.dmaNum); abort(); } memset (&cpdmaCfg, 0, sizeof (Cppi_CpDmaInitCfg)); cpdmaCfg.dmaNum = Cppi_CpDma_FFTC_B_CPDMA; if ((hCppi[1] = Cppi_open (&cpdmaCfg)) == NULL){ printf ("Error initializing CPPI for FFTC CPDMA %d\n", cpdmaCfg.dmaNum); abort(); } /* Disable FFTC CDMA loopback */ if (Cppi_setCpdmaLoopback (hCppi[1], 0) != CPPI_SOK){ printf ("Error disabling loopback for FFTC CPDMA %d\n", cpdmaCfg.dmaNum); abort(); } fftc_a_cfg_regs->CONFIG = 0; fftc_b_cfg_regs->CONFIG = 0; // CSL_FMK (FFTC_CONFIG_Q3_FLOWID_OVERWRITE, 0) | // CSL_FMK (FFTC_CONFIG_Q2_FLOWID_OVERWRITE, 0) | // CSL_FMK (FFTC_CONFIG_Q1_FLOWID_OVERWRITE, 0) | // CSL_FMK (FFTC_CONFIG_Q0_FLOWID_OVERWRITE, 0) | // CSL_FMK (FFTC_CONFIG_STARVATION_PERIOD, 0) | // CSL_FMK (FFTC_CONFIG_QUEUE_3_PRIORITY, 0) | // CSL_FMK (FFTC_CONFIG_QUEUE_2_PRIORITY, 0) | // CSL_FMK (FFTC_CONFIG_QUEUE_1_PRIORITY, 0) | // CSL_FMK (FFTC_CONFIG_QUEUE_0_PRIORITY, 0) | // CSL_FMK (FFTC_CONFIG_FFT_DISABLE, 0); /* Emptying Queues */ /* Tx FFTC */ Qmss_queueEmpty(QMSS_FFTC_A_QUEUE_BASE); for(i=QUEUE_FIRST; i<=QUEUE_LAST; i++){ Qmss_queueEmpty(i); } /* Populate free queues */ for(i=0; i<DATA_DESC_NUM; i++){ Cppi_Desc* mono_pkt = (Cppi_Desc *) ((int)data_desc_base + i*DATA_DESC_SIZE); Osal_DescBeginMemAccess(mono_pkt, DATA_DESC_SIZE); Qmss_Queue freeQueue = {0, QUEUE_FREE_DATA}; Cppi_setDescType( mono_pkt, Cppi_DescType_MONOLITHIC); Cppi_setDataOffset( Cppi_DescType_MONOLITHIC, mono_pkt, PACKET_HEADER); Cppi_setPacketLen( Cppi_DescType_MONOLITHIC, mono_pkt, DATA_DESC_SIZE); Cppi_setReturnQueue(Cppi_DescType_MONOLITHIC, mono_pkt, freeQueue); /* Sync Descriptor */ Osal_DescEndMemAccess(mono_pkt, DATA_DESC_SIZE); Qmss_queuePushDescSize(QUEUE_FREE_DATA, mono_pkt, DATA_DESC_SIZE); } for(i=0; i<CTRL_DESC_NUM; i++){ Cppi_Desc* mono_pkt = (Cppi_Desc *) ((int)ctrl_desc_base + i*CTRL_DESC_SIZE); Osal_DescBeginMemAccess(mono_pkt, CTRL_DESC_SIZE); Qmss_Queue freeQueue = {0, QUEUE_FREE_DATA}; Cppi_setDescType( mono_pkt, Cppi_DescType_MONOLITHIC); Cppi_setDataOffset( Cppi_DescType_MONOLITHIC, mono_pkt, PACKET_HEADER); Cppi_setPacketLen( Cppi_DescType_MONOLITHIC, mono_pkt, CTRL_DESC_SIZE); Cppi_setReturnQueue(Cppi_DescType_MONOLITHIC, mono_pkt, freeQueue); /* Sync Descriptor */ Osal_DescEndMemAccess(mono_pkt, CTRL_DESC_SIZE); Qmss_queuePushDescSize(QUEUE_FREE_CTRL, mono_pkt, CTRL_DESC_SIZE); } for(i=0; i<TRACE_DESC_NUM; i++){ Cppi_Desc* mono_pkt = (Cppi_Desc *) ((int)trace_desc_base + i*TRACE_DESC_SIZE); Osal_DescBeginMemAccess(mono_pkt, TRACE_DESC_SIZE); Qmss_Queue freeQueue = {0, QUEUE_FREE_DATA}; Cppi_setDescType( mono_pkt, Cppi_DescType_MONOLITHIC); Cppi_setDataOffset( Cppi_DescType_MONOLITHIC, mono_pkt, PACKET_HEADER); Cppi_setPacketLen( Cppi_DescType_MONOLITHIC, mono_pkt, TRACE_DESC_SIZE); Cppi_setReturnQueue(Cppi_DescType_MONOLITHIC, mono_pkt, freeQueue); /* Sync Descriptor */ Osal_DescEndMemAccess(mono_pkt, TRACE_DESC_SIZE); Qmss_queuePushDescSize(QUEUE_FREE_TRACE, mono_pkt, TRACE_DESC_SIZE); } for(i=0; i<FFTC_DESC_NUM; i++){ Cppi_Desc * host_pkt = (Cppi_Desc *) ((int)fftc_desc_base + i*FFTC_DESC_SIZE); Osal_DescBeginMemAccess(host_pkt, FFTC_DESC_SIZE); memset(host_pkt, 0, FFTC_DESC_SIZE); Qmss_Queue queue = {0, QUEUE_FREE_FFTC}; Cppi_setDescType( host_pkt, Cppi_DescType_HOST); Cppi_setReturnPolicy( Cppi_DescType_HOST, host_pkt, Cppi_ReturnPolicy_RETURN_BUFFER); Cppi_setReturnPushPolicy( Cppi_DescType_HOST, host_pkt, Qmss_Location_TAIL); Cppi_setPSLocation( Cppi_DescType_HOST, host_pkt, Cppi_PSLoc_PS_IN_DESC); Cppi_setReturnQueue( Cppi_DescType_HOST, host_pkt, queue); ((Cppi_HostDesc*)host_pkt)->nextBDPtr = 0; /* Sync Descriptor */ Osal_DescEndMemAccess(host_pkt, FFTC_DESC_SIZE); Qmss_queuePushDescSize(QUEUE_FREE_FFTC,host_pkt,FFTC_DESC_SIZE); } configureRxFlow(0); configureRxFlow(1); configureTxChan(0); configureTxChan(1); configureRxChan(0); configureRxChan(1); /* Finally, enable the Tx channel so that we can start sending * data blocks to FFTC engine. */ Cppi_channelEnable (hCppiTxChan[0]); Cppi_channelEnable (hCppiTxChan[1]); Cppi_channelEnable (hCppiRxChan[0]); Cppi_channelEnable (hCppiRxChan[1]); configureFFTRegs(fftc_a_cfg_regs); configureFFTRegs(fftc_b_cfg_regs); }