void MachineVerifier::verifyLiveVariables() { assert(LiveVars && "Don't call verifyLiveVariables without LiveVars"); for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { unsigned Reg = TargetRegisterInfo::index2VirtReg(i); LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg); for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); MFI != MFE; ++MFI) { BBInfo &MInfo = MBBInfoMap[MFI]; // Our vregsRequired should be identical to LiveVariables' AliveBlocks if (MInfo.vregsRequired.count(Reg)) { if (!VI.AliveBlocks.test(MFI->getNumber())) { report("LiveVariables: Block missing from AliveBlocks", MFI); *OS << "Virtual register " << PrintReg(Reg) << " must be live through the block.\n"; } } else { if (VI.AliveBlocks.test(MFI->getNumber())) { report("LiveVariables: Block should not be in AliveBlocks", MFI); *OS << "Virtual register " << PrintReg(Reg) << " is not needed live through the block.\n"; } } } } }
void BT::runEdgeQueue(BitVector &BlockScanned) { while (!FlowQ.empty()) { CFGEdge Edge = FlowQ.front(); FlowQ.pop(); if (EdgeExec.count(Edge)) return; EdgeExec.insert(Edge); ReachedBB.insert(Edge.second); const MachineBasicBlock &B = *MF.getBlockNumbered(Edge.second); MachineBasicBlock::const_iterator It = B.begin(), End = B.end(); // Visit PHI nodes first. while (It != End && It->isPHI()) { const MachineInstr &PI = *It++; InstrExec.insert(&PI); visitPHI(PI); } // If this block has already been visited through a flow graph edge, // then the instructions have already been processed. Any updates to // the cells would now only happen through visitUsesOf... if (BlockScanned[Edge.second]) return; BlockScanned[Edge.second] = true; // Visit non-branch instructions. while (It != End && !It->isBranch()) { const MachineInstr &MI = *It++; InstrExec.insert(&MI); visitNonBranch(MI); } // If block end has been reached, add the fall-through edge to the queue. if (It == End) { MachineFunction::const_iterator BIt = B.getIterator(); MachineFunction::const_iterator Next = std::next(BIt); if (Next != MF.end() && B.isSuccessor(&*Next)) { int ThisN = B.getNumber(); int NextN = Next->getNumber(); FlowQ.push(CFGEdge(ThisN, NextN)); } } else { // Handle the remaining sequence of branches. This function will update // the work queue. visitBranchesFrom(*It); } } // while (!FlowQ->empty()) }
void MachineVerifier::verifyLiveIntervals() { assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts"); for (LiveIntervals::const_iterator LVI = LiveInts->begin(), LVE = LiveInts->end(); LVI != LVE; ++LVI) { const LiveInterval &LI = *LVI->second; // Spilling and splitting may leave unused registers around. Skip them. if (MRI->use_empty(LI.reg)) continue; // Physical registers have much weirdness going on, mostly from coalescing. // We should probably fix it, but for now just ignore them. if (TargetRegisterInfo::isPhysicalRegister(LI.reg)) continue; assert(LVI->first == LI.reg && "Invalid reg to interval mapping"); for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end(); I!=E; ++I) { VNInfo *VNI = *I; const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def); if (!DefVNI) { if (!VNI->isUnused()) { report("Valno not live at def and not marked unused", MF); *OS << "Valno #" << VNI->id << " in " << LI << '\n'; } continue; } if (VNI->isUnused()) continue; if (DefVNI != VNI) { report("Live range at def has different valno", MF); *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << " where valno #" << DefVNI->id << " is live in " << LI << '\n'; continue; } const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def); if (!MBB) { report("Invalid definition index", MF); *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << " in " << LI << '\n'; continue; } if (VNI->isPHIDef()) { if (VNI->def != LiveInts->getMBBStartIdx(MBB)) { report("PHIDef value is not defined at MBB start", MF); *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << ", not at the beginning of BB#" << MBB->getNumber() << " in " << LI << '\n'; } } else { // Non-PHI def. const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def); if (!MI) { report("No instruction at def index", MF); *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << " in " << LI << '\n'; } else if (!MI->modifiesRegister(LI.reg, TRI)) { report("Defining instruction does not modify register", MI); *OS << "Valno #" << VNI->id << " in " << LI << '\n'; } bool isEarlyClobber = false; if (MI) { for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(), MOE = MI->operands_end(); MOI != MOE; ++MOI) { if (MOI->isReg() && MOI->getReg() == LI.reg && MOI->isDef() && MOI->isEarlyClobber()) { isEarlyClobber = true; break; } } } // Early clobber defs begin at USE slots, but other defs must begin at // DEF slots. if (isEarlyClobber) { if (!VNI->def.isUse()) { report("Early clobber def must be at a USE slot", MF); *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << " in " << LI << '\n'; } } else if (!VNI->def.isDef()) { report("Non-PHI, non-early clobber def must be at a DEF slot", MF); *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << " in " << LI << '\n'; } } } for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) { const VNInfo *VNI = I->valno; assert(VNI && "Live range has no valno"); if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) { report("Foreign valno in live range", MF); I->print(*OS); *OS << " has a valno not in " << LI << '\n'; } if (VNI->isUnused()) { report("Live range valno is marked unused", MF); I->print(*OS); *OS << " in " << LI << '\n'; } const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start); if (!MBB) { report("Bad start of live segment, no basic block", MF); I->print(*OS); *OS << " in " << LI << '\n'; continue; } SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB); if (I->start != MBBStartIdx && I->start != VNI->def) { report("Live segment must begin at MBB entry or valno def", MBB); I->print(*OS); *OS << " in " << LI << '\n' << "Basic block starts at " << MBBStartIdx << '\n'; } const MachineBasicBlock *EndMBB = LiveInts->getMBBFromIndex(I->end.getPrevSlot()); if (!EndMBB) { report("Bad end of live segment, no basic block", MF); I->print(*OS); *OS << " in " << LI << '\n'; continue; } if (I->end != LiveInts->getMBBEndIdx(EndMBB)) { // The live segment is ending inside EndMBB const MachineInstr *MI = LiveInts->getInstructionFromIndex(I->end.getPrevSlot()); if (!MI) { report("Live segment doesn't end at a valid instruction", EndMBB); I->print(*OS); *OS << " in " << LI << '\n' << "Basic block starts at " << MBBStartIdx << '\n'; } else if (TargetRegisterInfo::isVirtualRegister(LI.reg) && !MI->readsVirtualRegister(LI.reg)) { // A live range can end with either a redefinition, a kill flag on a // use, or a dead flag on a def. // FIXME: Should we check for each of these? bool hasDeadDef = false; for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(), MOE = MI->operands_end(); MOI != MOE; ++MOI) { if (MOI->isReg() && MOI->getReg() == LI.reg && MOI->isDef() && MOI->isDead()) { hasDeadDef = true; break; } } if (!hasDeadDef) { report("Instruction killing live segment neither defines nor reads " "register", MI); I->print(*OS); *OS << " in " << LI << '\n'; } } } // Now check all the basic blocks in this live segment. MachineFunction::const_iterator MFI = MBB; // Is this live range the beginning of a non-PHIDef VN? if (I->start == VNI->def && !VNI->isPHIDef()) { // Not live-in to any blocks. if (MBB == EndMBB) continue; // Skip this block. ++MFI; } for (;;) { assert(LiveInts->isLiveInToMBB(LI, MFI)); // We don't know how to track physregs into a landing pad. if (TargetRegisterInfo::isPhysicalRegister(LI.reg) && MFI->isLandingPad()) { if (&*MFI == EndMBB) break; ++MFI; continue; } // Check that VNI is live-out of all predecessors. for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(), PE = MFI->pred_end(); PI != PE; ++PI) { SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI).getPrevSlot(); const VNInfo *PVNI = LI.getVNInfoAt(PEnd); if (VNI->isPHIDef() && VNI->def == LiveInts->getMBBStartIdx(MFI)) continue; if (!PVNI) { report("Register not marked live out of predecessor", *PI); *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber() << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live at " << PEnd << " in " << LI << '\n'; continue; } if (PVNI != VNI) { report("Different value live out of predecessor", *PI); *OS << "Valno #" << PVNI->id << " live out of BB#" << (*PI)->getNumber() << '@' << PEnd << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber() << '@' << LiveInts->getMBBStartIdx(MFI) << " in " << LI << '\n'; } } if (&*MFI == EndMBB) break; ++MFI; } } // Check the LI only has one connected component. if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { ConnectedVNInfoEqClasses ConEQ(*LiveInts); unsigned NumComp = ConEQ.Classify(&LI); if (NumComp > 1) { report("Multiple connected components in live interval", MF); *OS << NumComp << " components in " << LI << '\n'; for (unsigned comp = 0; comp != NumComp; ++comp) { *OS << comp << ": valnos"; for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end(); I!=E; ++I) if (comp == ConEQ.getEqClass(*I)) *OS << ' ' << (*I)->id; *OS << '\n'; } } } } }
void InterferenceCache::Entry::update(unsigned MBBNum) { SlotIndex Start, Stop; tie(Start, Stop) = Indexes->getMBBRange(MBBNum); // Use advanceTo only when possible. if (PrevPos != Start) { if (!PrevPos.isValid() || Start < PrevPos) for (unsigned i = 0, e = Iters.size(); i != e; ++i) Iters[i].find(Start); else for (unsigned i = 0, e = Iters.size(); i != e; ++i) Iters[i].advanceTo(Start); PrevPos = Start; } MachineFunction::const_iterator MFI = MF->getBlockNumbered(MBBNum); BlockInterference *BI = &Blocks[MBBNum]; ArrayRef<SlotIndex> RegMaskSlots; ArrayRef<const uint32_t*> RegMaskBits; for (;;) { BI->Tag = Tag; BI->First = BI->Last = SlotIndex(); // Check for first interference. for (unsigned i = 0, e = Iters.size(); i != e; ++i) { Iter &I = Iters[i]; if (!I.valid()) continue; SlotIndex StartI = I.start(); if (StartI >= Stop) continue; if (!BI->First.isValid() || StartI < BI->First) BI->First = StartI; } // Also check for register mask interference. RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum); RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum); SlotIndex Limit = BI->First.isValid() ? BI->First : Stop; for (unsigned i = 0, e = RegMaskSlots.size(); i != e && RegMaskSlots[i] < Limit; ++i) if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) { // Register mask i clobbers PhysReg before the LIU interference. BI->First = RegMaskSlots[i]; break; } PrevPos = Stop; if (BI->First.isValid()) break; // No interference in this block? Go ahead and precompute the next block. if (++MFI == MF->end()) return; MBBNum = MFI->getNumber(); BI = &Blocks[MBBNum]; if (BI->Tag == Tag) return; tie(Start, Stop) = Indexes->getMBBRange(MBBNum); } // Check for last interference in block. for (unsigned i = 0, e = Iters.size(); i != e; ++i) { Iter &I = Iters[i]; if (!I.valid() || I.start() >= Stop) continue; I.advanceTo(Stop); bool Backup = !I.valid() || I.start() >= Stop; if (Backup) --I; SlotIndex StopI = I.stop(); if (!BI->Last.isValid() || StopI > BI->Last) BI->Last = StopI; if (Backup) ++I; } // Also check for register mask interference. SlotIndex Limit = BI->Last.isValid() ? BI->Last : Start; for (unsigned i = RegMaskSlots.size(); i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i) if (MachineOperand::clobbersPhysReg(RegMaskBits[i-1], PhysReg)) { // Register mask i-1 clobbers PhysReg after the LIU interference. // Model the regmask clobber as a dead def. BI->Last = RegMaskSlots[i-1].getDeadSlot(); break; } }
void BT::run() { reset(); assert(FlowQ.empty()); typedef GraphTraits<const MachineFunction*> MachineFlowGraphTraits; const MachineBasicBlock *Entry = MachineFlowGraphTraits::getEntryNode(&MF); unsigned MaxBN = 0; for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E; ++I) { assert(I->getNumber() >= 0 && "Disconnected block"); unsigned BN = I->getNumber(); if (BN > MaxBN) MaxBN = BN; } // Keep track of visited blocks. BitVector BlockScanned(MaxBN+1); int EntryN = Entry->getNumber(); // Generate a fake edge to get something to start with. FlowQ.push(CFGEdge(-1, EntryN)); while (!FlowQ.empty()) { CFGEdge Edge = FlowQ.front(); FlowQ.pop(); if (EdgeExec.count(Edge)) continue; EdgeExec.insert(Edge); const MachineBasicBlock &B = *MF.getBlockNumbered(Edge.second); MachineBasicBlock::const_iterator It = B.begin(), End = B.end(); // Visit PHI nodes first. while (It != End && It->isPHI()) { const MachineInstr &PI = *It++; InstrExec.insert(&PI); visitPHI(PI); } // If this block has already been visited through a flow graph edge, // then the instructions have already been processed. Any updates to // the cells would now only happen through visitUsesOf... if (BlockScanned[Edge.second]) continue; BlockScanned[Edge.second] = true; // Visit non-branch instructions. while (It != End && !It->isBranch()) { const MachineInstr &MI = *It++; InstrExec.insert(&MI); visitNonBranch(MI); } // If block end has been reached, add the fall-through edge to the queue. if (It == End) { MachineFunction::const_iterator BIt = B.getIterator(); MachineFunction::const_iterator Next = std::next(BIt); if (Next != MF.end() && B.isSuccessor(&*Next)) { int ThisN = B.getNumber(); int NextN = Next->getNumber(); FlowQ.push(CFGEdge(ThisN, NextN)); } } else { // Handle the remaining sequence of branches. This function will update // the work queue. visitBranchesFrom(*It); } } // while (!FlowQ->empty()) if (Trace) print_cells(dbgs() << "Cells after propagation:\n"); }
void MachineVerifier::verifyLiveIntervals() { assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts"); for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { unsigned Reg = TargetRegisterInfo::index2VirtReg(i); // Spilling and splitting may leave unused registers around. Skip them. if (MRI->reg_nodbg_empty(Reg)) continue; if (!LiveInts->hasInterval(Reg)) { report("Missing live interval for virtual register", MF); *OS << PrintReg(Reg, TRI) << " still has defs or uses\n"; continue; } const LiveInterval &LI = LiveInts->getInterval(Reg); assert(Reg == LI.reg && "Invalid reg to interval mapping"); for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end(); I!=E; ++I) { VNInfo *VNI = *I; const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def); if (!DefVNI) { if (!VNI->isUnused()) { report("Valno not live at def and not marked unused", MF); *OS << "Valno #" << VNI->id << " in " << LI << '\n'; } continue; } if (VNI->isUnused()) continue; if (DefVNI != VNI) { report("Live range at def has different valno", MF); *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << " where valno #" << DefVNI->id << " is live in " << LI << '\n'; continue; } const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def); if (!MBB) { report("Invalid definition index", MF); *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << " in " << LI << '\n'; continue; } if (VNI->isPHIDef()) { if (VNI->def != LiveInts->getMBBStartIdx(MBB)) { report("PHIDef value is not defined at MBB start", MF); *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << ", not at the beginning of BB#" << MBB->getNumber() << " in " << LI << '\n'; } } else { // Non-PHI def. const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def); if (!MI) { report("No instruction at def index", MF); *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << " in " << LI << '\n'; continue; } bool hasDef = false; bool isEarlyClobber = false; for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) { if (!MOI->isReg() || !MOI->isDef()) continue; if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { if (MOI->getReg() != LI.reg) continue; } else { if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) || !TRI->regsOverlap(LI.reg, MOI->getReg())) continue; } hasDef = true; if (MOI->isEarlyClobber()) isEarlyClobber = true; } if (!hasDef) { report("Defining instruction does not modify register", MI); *OS << "Valno #" << VNI->id << " in " << LI << '\n'; } // Early clobber defs begin at USE slots, but other defs must begin at // DEF slots. if (isEarlyClobber) { if (!VNI->def.isEarlyClobber()) { report("Early clobber def must be at an early-clobber slot", MF); *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << " in " << LI << '\n'; } } else if (!VNI->def.isRegister()) { report("Non-PHI, non-early clobber def must be at a register slot", MF); *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << " in " << LI << '\n'; } } } for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) { const VNInfo *VNI = I->valno; assert(VNI && "Live range has no valno"); if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) { report("Foreign valno in live range", MF); I->print(*OS); *OS << " has a valno not in " << LI << '\n'; } if (VNI->isUnused()) { report("Live range valno is marked unused", MF); I->print(*OS); *OS << " in " << LI << '\n'; } const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start); if (!MBB) { report("Bad start of live segment, no basic block", MF); I->print(*OS); *OS << " in " << LI << '\n'; continue; } SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB); if (I->start != MBBStartIdx && I->start != VNI->def) { report("Live segment must begin at MBB entry or valno def", MBB); I->print(*OS); *OS << " in " << LI << '\n' << "Basic block starts at " << MBBStartIdx << '\n'; } const MachineBasicBlock *EndMBB = LiveInts->getMBBFromIndex(I->end.getPrevSlot()); if (!EndMBB) { report("Bad end of live segment, no basic block", MF); I->print(*OS); *OS << " in " << LI << '\n'; continue; } // No more checks for live-out segments. if (I->end == LiveInts->getMBBEndIdx(EndMBB)) continue; // The live segment is ending inside EndMBB const MachineInstr *MI = LiveInts->getInstructionFromIndex(I->end.getPrevSlot()); if (!MI) { report("Live segment doesn't end at a valid instruction", EndMBB); I->print(*OS); *OS << " in " << LI << '\n' << "Basic block starts at " << MBBStartIdx << '\n'; continue; } // The block slot must refer to a basic block boundary. if (I->end.isBlock()) { report("Live segment ends at B slot of an instruction", MI); I->print(*OS); *OS << " in " << LI << '\n'; } if (I->end.isDead()) { // Segment ends on the dead slot. // That means there must be a dead def. if (!SlotIndex::isSameInstr(I->start, I->end)) { report("Live segment ending at dead slot spans instructions", MI); I->print(*OS); *OS << " in " << LI << '\n'; } } // A live segment can only end at an early-clobber slot if it is being // redefined by an early-clobber def. if (I->end.isEarlyClobber()) { if (I+1 == E || (I+1)->start != I->end) { report("Live segment ending at early clobber slot must be " "redefined by an EC def in the same instruction", MI); I->print(*OS); *OS << " in " << LI << '\n'; } } // The following checks only apply to virtual registers. Physreg liveness // is too weird to check. if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { // A live range can end with either a redefinition, a kill flag on a // use, or a dead flag on a def. bool hasRead = false; bool hasDeadDef = false; for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) { if (!MOI->isReg() || MOI->getReg() != LI.reg) continue; if (MOI->readsReg()) hasRead = true; if (MOI->isDef() && MOI->isDead()) hasDeadDef = true; } if (I->end.isDead()) { if (!hasDeadDef) { report("Instruction doesn't have a dead def operand", MI); I->print(*OS); *OS << " in " << LI << '\n'; } } else { if (!hasRead) { report("Instruction ending live range doesn't read the register", MI); I->print(*OS); *OS << " in " << LI << '\n'; } } } // Now check all the basic blocks in this live segment. MachineFunction::const_iterator MFI = MBB; // Is this live range the beginning of a non-PHIDef VN? if (I->start == VNI->def && !VNI->isPHIDef()) { // Not live-in to any blocks. if (MBB == EndMBB) continue; // Skip this block. ++MFI; } for (;;) { assert(LiveInts->isLiveInToMBB(LI, MFI)); // We don't know how to track physregs into a landing pad. if (TargetRegisterInfo::isPhysicalRegister(LI.reg) && MFI->isLandingPad()) { if (&*MFI == EndMBB) break; ++MFI; continue; } // Is VNI a PHI-def in the current block? bool IsPHI = VNI->isPHIDef() && VNI->def == LiveInts->getMBBStartIdx(MFI); // Check that VNI is live-out of all predecessors. for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(), PE = MFI->pred_end(); PI != PE; ++PI) { SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI); const VNInfo *PVNI = LI.getVNInfoBefore(PEnd); // All predecessors must have a live-out value. if (!PVNI) { report("Register not marked live out of predecessor", *PI); *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber() << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before " << PEnd << " in " << LI << '\n'; continue; } // Only PHI-defs can take different predecessor values. if (!IsPHI && PVNI != VNI) { report("Different value live out of predecessor", *PI); *OS << "Valno #" << PVNI->id << " live out of BB#" << (*PI)->getNumber() << '@' << PEnd << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber() << '@' << LiveInts->getMBBStartIdx(MFI) << " in " << PrintReg(Reg) << ": " << LI << '\n'; } } if (&*MFI == EndMBB) break; ++MFI; } } // Check the LI only has one connected component. if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { ConnectedVNInfoEqClasses ConEQ(*LiveInts); unsigned NumComp = ConEQ.Classify(&LI); if (NumComp > 1) { report("Multiple connected components in live interval", MF); *OS << NumComp << " components in " << LI << '\n'; for (unsigned comp = 0; comp != NumComp; ++comp) { *OS << comp << ": valnos"; for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end(); I!=E; ++I) if (comp == ConEQ.getEqClass(*I)) *OS << ' ' << (*I)->id; *OS << '\n'; } } } } }
void InterferenceCache::Entry::update(unsigned MBBNum) { SlotIndex Start, Stop; tie(Start, Stop) = Indexes->getMBBRange(MBBNum); // Use advanceTo only when possible. if (PrevPos != Start) { if (!PrevPos.isValid() || Start < PrevPos) for (unsigned i = 0, e = Iters.size(); i != e; ++i) Iters[i].find(Start); else for (unsigned i = 0, e = Iters.size(); i != e; ++i) Iters[i].advanceTo(Start); PrevPos = Start; } MachineFunction::const_iterator MFI = MF->getBlockNumbered(MBBNum); BlockInterference *BI = &Blocks[MBBNum]; for (;;) { BI->Tag = Tag; BI->First = BI->Last = SlotIndex(); // Check for first interference. for (unsigned i = 0, e = Iters.size(); i != e; ++i) { Iter &I = Iters[i]; if (!I.valid()) continue; SlotIndex StartI = I.start(); if (StartI >= Stop) continue; if (!BI->First.isValid() || StartI < BI->First) BI->First = StartI; } PrevPos = Stop; if (BI->First.isValid()) break; // No interference in this block? Go ahead and precompute the next block. if (++MFI == MF->end()) return; MBBNum = MFI->getNumber(); BI = &Blocks[MBBNum]; if (BI->Tag == Tag) return; tie(Start, Stop) = Indexes->getMBBRange(MBBNum); } // Check for last interference in block. for (unsigned i = 0, e = Iters.size(); i != e; ++i) { Iter &I = Iters[i]; if (!I.valid() || I.start() >= Stop) continue; I.advanceTo(Stop); bool Backup = !I.valid() || I.start() >= Stop; if (Backup) --I; SlotIndex StopI = I.stop(); if (!BI->Last.isValid() || StopI > BI->Last) BI->Last = StopI; if (Backup) ++I; } }