/**
* Enable Power Status Indicator (PSI)
*
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
InitializePsiFeature (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AP_TASK TaskPtr;
AGESA_STATUS AgesaStatus;
AMD_CPU_EARLY_PARAMS CpuEarlyParams;
IDS_HDT_CONSOLE (CPU_TRACE, " PSI mode is being initialized\n");
CpuEarlyParams.PlatformConfig = *PlatformConfig;
TaskPtr.FuncAddress.PfApTaskIOC = EnablePsiOnSocket;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &EntryPoint;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = PASS_EARLY_PARAMS | TASK_HAS_OUTPUT;
AgesaStatus = OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
IDS_HDT_CONSOLE (CPU_TRACE, " PSI mode is enabled\n");
return AgesaStatus;
}
/**
* Enable Message-based C1e
*
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
InitializeMsgBasedC1eFeature (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AP_TASK TaskPtr;
AMD_CPU_EARLY_PARAMS CpuEarlyParams;
IDS_HDT_CONSOLE (CPU_TRACE, " MT C1e is enabled\n");
if ((EntryPoint != CPU_FEAT_AFTER_PM_INIT) || (IsWarmReset (StdHeader))) {
CpuEarlyParams.PlatformConfig = *PlatformConfig;
TaskPtr.FuncAddress.PfApTaskIC = EnableMsgC1eOnSocket;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &EntryPoint;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
}
return AGESA_SUCCESS;
}
/**
* Perform the "BIOS Requirements for P-State Initialization and Transitions."
*
* This is the generic arbiter code to be executed by the BSC. The system power
* management init tables will be traversed. This must be run by the system BSC
* only.
*
* @param[in] CpuEarlyParams Required input parameters for early CPU initialization
* @param[in] StdHeader Config handle for library and services
*
* @return Most severe AGESA_STATUS level that any system processor encountered
*
*/
AGESA_STATUS
PmInitializationAtEarly (
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
UINT8 NumberOfSystemWideSteps;
AP_TASK TaskPtr;
AGESA_STATUS ReturnCode;
WARM_RESET_REQUEST Request;
// Determine the number of steps to perform
OptionMultiSocketConfiguration.GetNumberOfSystemPmSteps (&NumberOfSystemWideSteps, StdHeader);
// Traverse the PM init table
TaskPtr.FuncAddress.PfApTaskIC = PerformThisPmStep;
TaskPtr.DataTransfer.DataSizeInDwords = 1;
TaskPtr.DataTransfer.DataPtr = &i;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
for (i = 0; i < NumberOfSystemWideSteps; ++i) {
IDS_HDT_CONSOLE (CPU_TRACE, " Perform PM init step %d\n", i);
OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams);
}
// GoToMemInitPstateCore0 only if there is no pending warm reset.
GetWarmResetFlag (StdHeader, &Request);
if (Request.RequestBit == FALSE) {
TaskPtr.FuncAddress.PfApTaskC = GoToMemInitPstateCore0;
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
IDS_HDT_CONSOLE (CPU_TRACE, " Transition all cores to POST P-state\n");
OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams);
}
// Retrieve/Process any errors
ReturnCode = OptionMultiSocketConfiguration.BscRetrievePmEarlyInitErrors (StdHeader);
return (ReturnCode);
}
/**
*
* InitializeCacheFlushOnHaltFeature
*
* CPU feature leveling. Enable Cpu Cache Flush On Halt Function
*
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in,out] StdHeader Pointer to AMD_CONFIG_PARAMS struct.
*
* @return The most severe status of any family specific service.
*/
AGESA_STATUS
InitializeCacheFlushOnHaltFeature (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AP_TASK TaskPtr;
AMD_CPU_EARLY_PARAMS CpuEarlyParams;
CpuEarlyParams.PlatformConfig = *PlatformConfig;
IDS_HDT_CONSOLE (CPU_TRACE, " Cache flush on hlt feature is enabled\n");
TaskPtr.FuncAddress.PfApTaskIC = EnableCacheFlushOnHaltOnSocket;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &EntryPoint;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
return AGESA_SUCCESS;
}
/**
* Enable the C6 C-state
*
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
InitializeC6Feature (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 BscSocket;
UINT32 Ignored;
UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
UINT32 NumberOfCores;
AP_TASK TaskPtr;
AMD_CPU_EARLY_PARAMS CpuEarlyParams;
C6_FAMILY_SERVICES *C6FamilyServices;
AGESA_STATUS IgnoredSts;
CpuEarlyParams.PlatformConfig = *PlatformConfig;
TaskPtr.FuncAddress.PfApTaskIC = EnableC6OnSocket;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &EntryPoint;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
if (((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) &&
!(IsSecureS3 (StdHeader))) {
// Load any required microcode patches on both normal boot and resume from S3.
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
GetFeatureServicesOfSocket (&C6FamilyServiceTable, BscSocket, (CONST VOID **)&C6FamilyServices, StdHeader);
if (C6FamilyServices != NULL) {
C6FamilyServices->ReloadMicrocodePatchAfterMemInit (StdHeader);
}
// run code on all APs
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.ExeFlags = 0;
NumberOfSockets = GetPlatformNumberOfSockets ();
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (CONST VOID **)&C6FamilyServices, StdHeader);
if (C6FamilyServices != NULL) {
// run code on all APs
TaskPtr.FuncAddress.PfApTask = C6FamilyServices->ReloadMicrocodePatchAfterMemInit;
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
}
}
}
}
}
return AGESA_SUCCESS;
}
