/** * Enable DA-C Cpu Cache Flush On Halt Function * * @param[in] FamilySpecificServices The current Family Specific Services. * @param[in] EntryPoint Timepoint designator. * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. */ VOID SetF10DaCacheFlushOnHaltRegister ( IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, IN UINT64 EntryPoint, IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 CoreCount; UINT32 AndMask; UINT32 OrMask; PCI_ADDR PciAddress; CPU_LOGICAL_ID LogicalId; if ((EntryPoint & CPU_FEAT_AFTER_POST_MTRR_SYNC) != 0) { // F3xDC[25:19] = 04h // F3xDC[18:16] = 111b PciAddress.Address.Function = FUNC_3; PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG; AndMask = 0xFC00FFFF; OrMask = 0x00270000; GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); if (LogicalId.Revision == AMD_F10_DA_C2) { //For DA_C2 single Core, F3xDC[18:16] = 0 GetActiveCoresInCurrentSocket (&CoreCount, StdHeader); if (CoreCount == 1) { OrMask = 0x00200000; } } IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader); OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC } }
/** * Entry point for enabling Application Power Management * * This function must be run after all P-State routines have been executed * * @param[in] ApmServices The current CPU's family services. * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config handle for library and services. * * @retval AGESA_SUCCESS Always succeeds. * */ AGESA_STATUS STATIC F15InitializeApm ( IN APM_FAMILY_SERVICES *ApmServices, IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 LocalPciRegister; PCI_ADDR PciAddress; PciAddress.Address.Function = FUNC_4; PciAddress.Address.Register = CPB_CTRL_REG; LocalPciRegister = 0; ((F15_CPB_CTRL_REGISTER *) (&LocalPciRegister))->ApmMasterEn = 1; OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, 0xFFFFFFFF, LocalPciRegister, StdHeader); return AGESA_SUCCESS; }
/** * Family 15h core 0 entry point for performing the family 15h Processor- * Systemboard Power Delivery Check. * * The steps are as follows: * 1. Starting with P0, loop through all P-states until a passing state is * found. A passing state is one in which the current required by the * CPU is less than the maximum amount of current that the system can * provide to the CPU. If P0 is under the limit, no further action is * necessary. * 2. If at least one P-State is under the limit & at least one P-State is * over the limit, the BIOS must: * a. If the processor's current P-State is disabled by the power check, * then the BIOS must request a transition to an enabled P-state * using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate] * to reflect the new value. * b. Copy the contents of the enabled P-state MSRs to the highest * performance P-state locations. * c. Request a P-state transition to the P-state MSR containing the * COF/VID values currently applied. * d. If a subset of boosted P-states are disabled, then copy the contents * of the highest performance boosted P-state still enabled to the * boosted P-states that have been disabled. * e. If all boosted P-states are disabled, then program D18F4x15C[BoostSrc] * to zero. * f. Adjust the following P-state parameters affected by the P-state * MSR copy by subtracting the number of P-states that are disabled * by the power check. * 1. F3x64[HtcPstateLimit] * 2. F3x68[SwPstateLimit] * 3. F3xDC[PstateMaxVal] * 3. If all P-States are over the limit, the BIOS must: * a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then * write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for * MSRC001_0063[CurPstate] to reflect the new value. * b. If MSRC001_0061[PstateMaxVal]!=000b, copy the contents of the P-state * MSR pointed to by F3xDC[PstateMaxVal] to the software P0 MSR. * Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063 * [CurPstate] to reflect the new value. * c. Adjust the following P-state parameters to zero: * 1. F3x64[HtcPstateLimit] * 2. F3x68[SwPstateLimit] * 3. F3xDC[PstateMaxVal] * d. Program D18F4x15C[BoostSrc] to zero. * * @param[in] FamilySpecificServices The current Family Specific Services. * @param[in] CpuEarlyParams Service parameters * @param[in] StdHeader Config handle for library and services. * */ VOID F15PmPwrCheck ( IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT8 DisPsNum; UINT8 PsMaxVal; UINT8 Pstate; UINT32 ProcIddMax; UINT32 LocalPciRegister; UINT32 Socket; UINT32 Module; UINT32 Core; UINT32 AndMask; UINT32 OrMask; UINT32 PstateLimit; PCI_ADDR PciAddress; UINT64 LocalMsrRegister; AP_TASK TaskPtr; AGESA_STATUS IgnoredSts; PWRCHK_ERROR_DATA ErrorData; UINT32 NumModules; UINT32 HighCore; UINT32 LowCore; UINT32 ModuleIndex; // get the socket number IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); ErrorData.SocketNumber = (UINT8) Socket; ASSERT (Core == 0); // get the Max P-state value for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) { LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader); if (((F15_PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { break; } } ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1); // Starting with P0, loop through all P-states until a passing state is // found. A passing state is one in which the current required by the // CPU is less than the maximum amount of current that the system can // provide to the CPU. If P0 is under the limit, no further action is // necessary. DisPsNum = 0; for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) { if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) { if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) { // Add to event log the Pstate that exceeded the current limit PutEventLog (AGESA_WARNING, CPU_EVENT_PM_PSTATE_OVERCURRENT, Socket, Pstate, 0, 0, StdHeader); DisPsNum++; } else { break; } } } ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum); if (ErrorData.AllowablePstateNumber == 0) { PutEventLog (AGESA_FATAL, CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT, Socket, 0, 0, 0, StdHeader); } if (DisPsNum != 0) { GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); PciAddress.Address.Function = FUNC_4; PciAddress.Address.Register = CPB_CTRL_REG; LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C ErrorData.NumberOfBoostStates = (UINT8) ((F15_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; if (DisPsNum >= ErrorData.NumberOfBoostStates) { // If all boosted P-states are disabled, then program D18F4x15C[BoostSrc] to zero. AndMask = 0xFFFFFFFF; ((F15_CPB_CTRL_REGISTER *) &AndMask)->BoostSrc = 0; OrMask = 0x00000000; OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x15C // Update the result of isFeatureEnabled in heap. UpdateFeatureStatusInHeap (CoreBoost, FALSE, StdHeader); ErrorData.NumberOfSwPstatesDisabled = DisPsNum - ErrorData.NumberOfBoostStates; } else { ErrorData.NumberOfSwPstatesDisabled = 0; } NumModules = GetPlatformNumberOfModules (); // Only execute this loop if this is an MCM. if (NumModules > 1) { // Since the P-State MSRs are shared across a // node, we only need to set one core in the node for the modified number of supported p-states // to be reported across all of the cores in the module. TaskPtr.FuncAddress.PfApTaskI = F15PmPwrCheckCore; TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA); TaskPtr.DataTransfer.DataPtr = &ErrorData; TaskPtr.DataTransfer.DataTransferFlags = 0; TaskPtr.ExeFlags = WAIT_FOR_CORE; for (ModuleIndex = 0; ModuleIndex < NumModules; ModuleIndex++) { // Execute the P-State reduction code on the module's primary core only. // Skip this code for the BSC's module. if (ModuleIndex != Module) { if (GetGivenModuleCoreRange (Socket, ModuleIndex, &LowCore, &HighCore, StdHeader)) { ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)LowCore, &TaskPtr, StdHeader); } } } } // Path for SCM and the BSC F15PmPwrCheckCore (&ErrorData, StdHeader); // Final Step // F3x64[HtPstatelimit] -= disPsNum // F3x68[SwPstateLimit] -= disPsNum // F3xDC[PstateMaxVal] -= disPsNum PciAddress.Address.Function = FUNC_3; PciAddress.Address.Register = HTC_REG; AndMask = 0xFFFFFFFF; ((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0; OrMask = 0x00000000; LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x64 PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit; if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit; } OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x64 PciAddress.Address.Register = SW_PS_LIMIT_REG; AndMask = 0xFFFFFFFF; ((SW_PS_LIMIT_REGISTER *) &AndMask)->SwPstateLimit = 0; OrMask = 0x00000000; LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x68 PstateLimit = ((SW_PS_LIMIT_REGISTER *) &LocalPciRegister)->SwPstateLimit; if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; ((SW_PS_LIMIT_REGISTER *) &OrMask)->SwPstateLimit = PstateLimit; } OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x68 PciAddress.Address.Register = CPTC2_REG; AndMask = 0xFFFFFFFF; ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0; OrMask = 0x00000000; LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xDC PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal; if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit; } OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC } }