/**
* Family specific call to check if PSD need to be generated.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in,out] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE PSD need to be generated
* @retval FALSE PSD does NOT need to be generated
*
*/
BOOLEAN
STATIC
F15OrIsPstatePsdNeeded (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
PLATFORM_FEATS Features;
// Initialize the union
Features.PlatformValue = 0;
GetPlatformFeatures (&Features, PlatformConfig, StdHeader);
//
// For Single link processor, PSD needs to be generated
// For other processor, if D18F5x80[DualCore][0]=0, the _PSD object does not need to be generated.
//
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
PciAddress.Address.Register = COMPUTE_UNIT_STATUS;
PciAddress.Address.Function = FUNC_5;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if ((!Features.PlatformFeatures.PlatformSingleLink) && ((LocalPciRegister & 0x10000) == 0)) {
return FALSE;
}
return TRUE;
}
/**
* Set the Processor Name String register based on F5x194/198
*
* This function copies F5x198_x[B:0] to MSR_C001_00[35:30]
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[in] EarlyParams Service parameters.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F15SetBrandIdRegistersAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 PciData;
UINT32 ExceptionId;
UINT32 MsrIndex;
UINT64 MsrData;
UINT64 *MsrNameStringPtrPtr;
PCI_ADDR PciAddress;
if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
if (IsException (&ExceptionId, StdHeader)) {
ASSERT (ExceptionId < (sizeof (CpuF15ExceptionBrandIdString) / sizeof (CpuF15ExceptionBrandIdString[0])));
MsrNameStringPtrPtr = (UINT64 *) CpuF15ExceptionBrandIdString[ExceptionId].Stringstart;
} else {
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
PciAddress.Address.Function = FUNC_5;
PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
// check if D18F5x198_x0 is 00000000h.
PciData = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
PciAddress.Address.Register = NAME_STRING_DATA_PORT;
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
if (PciData != 0) {
for (MsrIndex = 0; MsrIndex <= (MSR_CPUID_NAME_STRING5 - MSR_CPUID_NAME_STRING0); MsrIndex++) {
PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
PciData = MsrIndex * 2;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
PciAddress.Address.Register = NAME_STRING_DATA_PORT;
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
((PROCESSOR_NAME_STRING *) (&MsrData))->lo = PciData;
PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
PciData = (MsrIndex * 2) + 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
PciAddress.Address.Register = NAME_STRING_DATA_PORT;
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
((PROCESSOR_NAME_STRING *) (&MsrData))->hi = PciData;
LibAmdMsrWrite ((MsrIndex + MSR_CPUID_NAME_STRING0), &MsrData, StdHeader);
}
return;
} else {
// It is unprogrammed (unfused) parts and use a name string of "AMD Unprogrammed Engineering Sample"
MsrNameStringPtrPtr = (UINT64 *) str_Unprogrammed_Sample;
}
}
// Put values into name MSRs, Always write the full 48 bytes
for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) {
LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader);
MsrNameStringPtrPtr++;
}
}
}
/**
* Support routine for F15OrPmNbAfterReset to perform MSR initialization on one
* core of each die in a family 15h socket.
*
* This function implements steps 1 - 13 on each core.
*
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F15OrPmNbAfterResetOnCore (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NbPsCtrlOnEntry;
UINT32 NbPsCtrlOnExit;
UINT64 LocalMsrRegister;
PCI_ADDR PciAddress;
// 1. Temp1 = D18F5x170[SwNbPstateLoDis].
// 2. Temp2 = D18F5x170[NbPstateDisOnP0].
// 3. Temp3 = D18F5x170[NbPstateThreshold].
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
PciAddress.Address.Function = FUNC_5;
PciAddress.Address.Register = NB_PSTATE_CTRL;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnEntry, StdHeader);
// Check if NB P-states were disabled, and if so, prevent any changes from occurring.
if (((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateMaxVal != 0) {
// 4. If MSRC001_0070[NbPstate] = 1, go to step 9
LibAmdMsrRead (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader);
if (((COFVID_CTRL_MSR *) &LocalMsrRegister)->NbPstate == 0) {
// 5. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
// 6. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
TransitionToNbLow (PciAddress, StdHeader);
// 7. Set D18F5x170[SwNbPstateLoDis] = 1.
// 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
// Go to step 13.
TransitionToNbHigh (PciAddress, StdHeader);
} else {
// 9. Set D18F5x170[SwNbPstateLoDis] = 1.
// 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
TransitionToNbHigh (PciAddress, StdHeader);
// 11. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
// 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
TransitionToNbLow (PciAddress, StdHeader);
}
// 13. Set D18F5x170[SwNbPstateLoDis] = Temp1, D18F5x170[NbPstateDisOnP0] = Temp2, and
// D18F5x170[NbPstateThreshold] = Temp3.
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis;
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateDisOnP0;
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateThreshold;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
}
}
/**
* Entry point for enabling Power Status Indicator
*
* This function must be run after all P-State routines have been executed
*
* @param[in] PsiServices The current CPU's family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F15TnInitializePsi (
IN PSI_FAMILY_SERVICES *PsiServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
// Configure PsiVid
F15TnPmVrmLowPowerModeEnable (FamilySpecificServices, PlatformConfig, PciAddress, StdHeader);
}
return AGESA_SUCCESS;
}
