bool isSpareBitOnDMIBus( ExtensibleChip * i_mcsChip, ExtensibleChip * i_mbChip )
{
bool bitOn = false;
do
{
// If any of these object is NULL, spare bit should not be on.
if ( ( NULL == i_mcsChip ) || ( NULL == i_mbChip ))
break;
// check spare deployed bit on Centaur side
SCAN_COMM_REGISTER_CLASS * dmiFir = i_mbChip->getRegister( "DMIFIR" );
int32_t rc = dmiFir->Read();
if ( SUCCESS != rc )
{
PRDF_ERR("isSpareBitOnDMIBus() : Failed to read DMIFIR."
"MEMBUF: 0x%08X", getHuid( i_mbChip->GetChipHandle()) );
break;
}
if ( dmiFir->IsBitSet( 9 ))
{
bitOn = true;
break;
}
// check spare deployed bit on Proc side
TargetHandle_t mcsTgt = i_mcsChip->GetChipHandle();
TargetHandle_t procTgt = getConnectedParent( mcsTgt, TYPE_PROC );
ExtensibleChip * procChip =
( ExtensibleChip * )systemPtr->GetChip( procTgt );
uint32_t mcsPos = getTargetPosition( mcsTgt );
const char * regStr = ( 4 > mcsPos) ? "IOMCFIR_0" : "IOMCFIR_1";
SCAN_COMM_REGISTER_CLASS * iomcFir = procChip->getRegister( regStr );
rc = iomcFir->Read();
if ( SUCCESS != rc )
{
PRDF_ERR("isSpareBitOnDMIBus() : Failed to read %s."
"MCS: 0x%08X", regStr, getHuid(mcsTgt) );
break;
}
// Bit 9, 17, 25 and 33 are for spare deployed.
// Check bit corrosponding to MCS position
uint8_t bitPos = 9 + ( mcsPos % 4 ) *8;
if ( iomcFir->IsBitSet(bitPos))
{
bitOn = true;
}
}while(0);
return bitOn;
}
/**
* @brief Query the PLL chip for a PCI PLL error
* @param i_chip P8 Pci chip
* @param o_result set to true in the presence of PLL error
* @returns Failure or Success of query.
*/
int32_t QueryPciPll( ExtensibleChip * i_chip,
bool & o_result)
{
#define PRDF_FUNC "[Proc::QueryPciPll] "
int32_t rc = SUCCESS;
o_result = false;
SCAN_COMM_REGISTER_CLASS * pciErrReg =
i_chip->getRegister("PCI_ERROR_REG");
SCAN_COMM_REGISTER_CLASS * pciConfigReg =
i_chip->getRegister("PCI_CONFIG_REG");
do
{
rc = pciErrReg->Read();
if (rc != SUCCESS)
{
PRDF_ERR(PRDF_FUNC "PCI_ERROR_REG read failed"
"for 0x%08x", i_chip->GetId());
break;
}
rc = pciConfigReg->Read();
if (rc != SUCCESS)
{
PRDF_ERR(PRDF_FUNC "PCI_CONFIG_REG read failed"
"for 0x%08x", i_chip->GetId());
break;
}
if(pciErrReg->IsBitSet(PLL_ERROR_BIT) &&
!pciConfigReg->IsBitSet(PLL_ERROR_MASK))
{
o_result = true;
}
} while(0);
if( rc != SUCCESS )
{
PRDF_ERR(PRDF_FUNC "failed for proc: 0x%.8X",
i_chip->GetId());
}
return rc;
#undef PRDF_FUNC
}
int32_t checkMcsChannelFail( ExtensibleChip * i_mcsChip,
STEP_CODE_DATA_STRUCT & io_sc )
{
#define PRDF_FUNC "[MemUtils::checkMcsChannelFail] "
int32_t o_rc = SUCCESS;
do
{
// Skip if already handling unit checkstop.
if ( io_sc.service_data->GetFlag(ServiceDataCollector::UNIT_CS) )
break;
// Must be an MCS.
if ( TYPE_MCS != getTargetType(i_mcsChip->GetChipHandle()) )
{
PRDF_ERR( PRDF_FUNC "i_mcsChip is not TYPE_MCS" );
o_rc = FAIL; break;
}
// Check MCIFIR[31] for presence of channel fail.
SCAN_COMM_REGISTER_CLASS * mcifir = i_mcsChip->getRegister("MCIFIR");
o_rc = mcifir->Read();
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "Read() failed on MCIFIR" );
break;
}
if ( !mcifir->IsBitSet(31) ) break; // No channel fail, so exit.
// Set unit checkstop flag and cause attention type.
io_sc.service_data->SetFlag(ServiceDataCollector::UNIT_CS);
io_sc.service_data->setSecondaryAttnType(UNIT_CS);
io_sc.service_data->SetThresholdMaskId(0);
// Indicate that cleanup is required.
P8McsDataBundle * mcsdb = getMcsDataBundle( i_mcsChip );
ExtensibleChip * membChip = mcsdb->getMembChip();
if ( NULL == membChip )
{
PRDF_ERR( PRDF_FUNC "getMembChip() returned NULL" );
o_rc = FAIL; break;
}
CenMembufDataBundle * mbdb = getMembufDataBundle( membChip );
mbdb->iv_doChnlFailCleanup = true;
} while (0);
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "Failed: i_mcsChip=0x%08x", i_mcsChip->GetId() );
}
return o_rc;
#undef PRDF_FUNC
}
uint32_t getIoOscPos( ExtensibleChip * i_chip,
STEP_CODE_DATA_STRUCT & io_sc)
{
#define PRDF_FUNC "[PLL::getIoOscPos] "
uint32_t o_oscPos = MAX_PCIE_OSC_PER_NODE;
do
{
int32_t rc = SUCCESS;
// START WORKAROUND
// TODO: RTC 137711 - This redundant clock code only applies to Brazos
// systems. Unfortunately, this code made it into the common
// source and we ran into SW324506 where we are unable to SCOM
// PCIE_OSC_SWITCH during OP checkstop analysis. We should have
// a system attribute that tells us if redundant clock are enabled
// but for now just assume anything that is OPAL based will not
// have redundant clocks. Note that we still need this code in
// Hostboot (not HBRT) because Hostboot is still run on a Brazos
// system.
if ( isHyprConfigOpal() )
{
o_oscPos = 0;
break;
}
// END WORKAROUND
SCAN_COMM_REGISTER_CLASS * pcieOscSwitchReg =
i_chip->getRegister("PCIE_OSC_SWITCH");
rc = pcieOscSwitchReg->Read();
if (rc != SUCCESS)
{
PRDF_ERR(PRDF_FUNC "PCIE_OSC_SWITCH read failed"
"for 0x%08x", i_chip->GetId());
break;
}
// [ 16 ] == 1 ( OSC 0 is active )
// [ 16 ] == 0 ( OSC 1 is active )
if(pcieOscSwitchReg->IsBitSet(16))
{
o_oscPos = 0;
}
else
{
o_oscPos = 1;
}
} while(0);
return o_oscPos;
#undef PRDF_FUNC
}
/**
* @brief Call to check for configured PHB (before capturing FFDC)
* @param i_chip P8 chip
* @param i_phbPos PHB position
* @param o_isPhbConfigured set to true if the PHB configured
* @returns Success
*/
int32_t phbConfigured(ExtensibleChip * i_chip,
uint32_t i_phbPos,
bool & o_isPhbConfigured)
{
#define PRDF_FUNC "[Proc::phbConfigured] "
static const uint32_t MAX_PCI_NUM = 3;
static const char * pciEtuResetReg[MAX_PCI_NUM] =
{ "PCI_ETU_RESET_0",
"PCI_ETU_RESET_1",
"PCI_ETU_RESET_2" };
int32_t o_rc = SUCCESS;
o_isPhbConfigured = false;
do
{
if( i_phbPos >= MAX_PCI_NUM )
{
PRDF_ERR( PRDF_FUNC"invalid PCI number: %d", i_phbPos );
break;
}
SCAN_COMM_REGISTER_CLASS * etuResetReg =
i_chip->getRegister( pciEtuResetReg[i_phbPos] );
if(NULL == etuResetReg)
{
PRDF_ERR( PRDF_FUNC"getRegister() Failed for register:%s",
pciEtuResetReg[i_phbPos] );
break;
}
o_rc = etuResetReg->Read();
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC"%s Read() failed. Target=0x%08x",
pciEtuResetReg[i_phbPos], i_chip->GetId() );
break;
}
// If bit 0 is cleared then the PHB is configured
if ( ! etuResetReg->IsBitSet(0) )
{
o_isPhbConfigured = true;
}
} while(0);
return SUCCESS;
#undef PRDF_FUNC
}
/**
* @brief Call to check for configured PHB (before capturing FFDC)
* @param i_chip P8 chip
* @param i_phbPos PHB position
* @param o_isPhbConfigured set to true if the PHB configured
* @returns Success
*/
int32_t phbConfigured( ExtensibleChip * i_chip, uint32_t i_phbPos,
bool & o_isPhbConfigured )
{
#define PRDF_FUNC "[Proc::phbConfigured] "
o_isPhbConfigured = false;
uint32_t maxPhbs = 3; // Murano/Venice
if ( MODEL_NAPLES == getProcModel(i_chip->GetChipHandle()) )
maxPhbs = 4;
do
{
if ( maxPhbs <= i_phbPos )
{
// This PHB doesn't exist, return false
break;
}
char reg_str[64];
snprintf( reg_str, 64, "PCI_ETU_RESET_%d", i_phbPos );
SCAN_COMM_REGISTER_CLASS * reg = i_chip->getRegister( reg_str );
if ( NULL == reg )
{
PRDF_ERR( PRDF_FUNC"getRegister() failed for %s", reg_str );
break;
}
int32_t l_rc = reg->Read();
if ( SUCCESS != l_rc )
{
PRDF_ERR( PRDF_FUNC"Read() failed for %s: target=0x%08x",
reg_str, i_chip->GetId() );
break;
}
// If bit 0 is cleared then the PHB is configured
if ( !reg->IsBitSet(0) )
{
o_isPhbConfigured = true;
}
} while(0);
return SUCCESS;
#undef PRDF_FUNC
}
int32_t checkMcsChannelFail( ExtensibleChip * i_mcsChip,
STEP_CODE_DATA_STRUCT & io_sc )
{
#define PRDF_FUNC "[MemUtils::checkMcsChannelFail] "
int32_t o_rc = SUCCESS;
do
{
// Skip if already handling unit checkstop.
if ( io_sc.service_data->GetFlag(ServiceDataCollector::UNIT_CS) )
break;
// Must be an MCS.
if ( TYPE_MCS != getTargetType(i_mcsChip->GetChipHandle()) )
{
PRDF_ERR( PRDF_FUNC"i_mcsChip is not TYPE_MCS" );
o_rc = FAIL; break;
}
// Check MCIFIR[31] for presence of channel fail.
SCAN_COMM_REGISTER_CLASS * mcifir = i_mcsChip->getRegister("MCIFIR");
o_rc = mcifir->Read();
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC"Read() failed on MCIFIR" );
break;
}
if ( !mcifir->IsBitSet(31) ) break; // No channel fail, so exit.
// Set unit checkstop flag and cause attention type.
io_sc.service_data->SetFlag(ServiceDataCollector::UNIT_CS);
io_sc.service_data->SetCauseAttentionType(UNIT_CS);
io_sc.service_data->SetThresholdMaskId(0);
} while (0);
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC"Failed: i_mcsChip=0x%08x", i_mcsChip->GetId() );
}
return o_rc;
#undef PRDF_FUNC
}
/**
* @brief Calls out the EX chiplet (MRU_LOW), if possible. Otherwise, calls
* out the PROC (MRU_LOW)
* @param i_chip P8 chip
* @param io_sc service data collector
* @returns SUCCESS
*/
int32_t combinedResponseCallout( ExtensibleChip * i_chip,
STEP_CODE_DATA_STRUCT & io_sc )
{
#define PRDF_FUNC "[Proc::combinedResponseCallout] "
int32_t l_rc = SUCCESS;
TargetHandle_t procTrgt = i_chip->GetChipHandle();
SCAN_COMM_REGISTER_CLASS * reg = i_chip->getRegister("PB_CENT_CR_ERROR");
do
{
l_rc = reg->Read();
if ( SUCCESS != l_rc )
{
PRDF_ERR( PRDF_FUNC"Read() failed on PB_CENT_CR_ERROR" );
break;
}
uint32_t tmp = reg->GetBitFieldJustified(0,3);
if ( 0x02 != tmp ) // Must be 0b010 to continue
{
PRDF_ERR( PRDF_FUNC"Unsupported reason code: 0x%02x", tmp );
l_rc = FAIL; break;
}
tmp = reg->GetBitFieldJustified(38,5);
if ( 0x00 != tmp ) // Must be 0b00000 to continue
{
PRDF_ERR( PRDF_FUNC"Unsupported combined response encoding: 0x%02x",
tmp );
l_rc = FAIL; break;
}
if ( reg->IsBitSet(22) ) // Must be 0b0 to continue
{
PRDF_ERR( PRDF_FUNC"Operation not sourced by an EX chiplet" );
l_rc = FAIL; break;
}
// Get the EX target
tmp = reg->GetBitFieldJustified(23,4);
TargetHandle_t exTrgt = getConnectedChild( procTrgt, TYPE_EX, tmp );
if ( NULL == exTrgt )
{
PRDF_ERR( PRDF_FUNC"No connected EX chiplet at position %d", tmp );
l_rc = FAIL; break;
}
// Callout the EX target
io_sc.service_data->SetCallout( exTrgt, MRU_LOW );
} while (0);
if ( SUCCESS != l_rc )
{
PRDF_ERR( PRDF_FUNC"Unable to isolate to an EX chiplet. Calling out "
"PROC 0x%08x instead.", i_chip->GetId() );
io_sc.service_data->SetCallout( procTrgt, MRU_LOW );
}
return SUCCESS;
#undef PRDF_FUNC
}
/**
* @brief Plugin to mask the side effects of an RCD parity error
* @param i_mbaChip A Centaur MBA chip.
* @param i_sc The step code data struct.
* @return SUCCESS
*/
int32_t maskRcdParitySideEffects( ExtensibleChip * i_mbaChip,
STEP_CODE_DATA_STRUCT & i_sc )
{
#define PRDF_FUNC "[maskRcdParitySideEffects] "
int32_t l_rc = SUCCESS;
do
{
//use a data bundle to get the membuf chip
CenMbaDataBundle * mbadb = getMbaDataBundle( i_mbaChip );
ExtensibleChip * membChip = mbadb->getMembChip();
if (NULL == membChip)
{
PRDF_ERR(PRDF_FUNC "getMembChip() failed");
break;
}
//get the FIRs
SCAN_COMM_REGISTER_CLASS * mbsFir =
membChip->getRegister("MBSFIR");
SCAN_COMM_REGISTER_CLASS * mbaCalFir =
i_mbaChip->getRegister("MBACALFIR");
SCAN_COMM_REGISTER_CLASS * mbaFir =
i_mbaChip->getRegister("MBAFIR");
l_rc = mbsFir->Read();
l_rc |= mbaCalFir->Read();
l_rc |= mbaFir->Read();
if (SUCCESS != l_rc)
{
PRDF_ERR(PRDF_FUNC "MBSFIR/MBACALFIR/MBAFIR read failed for"
" 0x%08x", i_mbaChip->GetId());
break;
}
//get the masks for each FIR
SCAN_COMM_REGISTER_CLASS * mbsFirMaskOr =
membChip->getRegister("MBSFIR_MASK_OR");
SCAN_COMM_REGISTER_CLASS * mbaCalMaskOr =
i_mbaChip->getRegister("MBACALFIR_MASK_OR");
SCAN_COMM_REGISTER_CLASS * mbaFirMaskOr =
i_mbaChip->getRegister("MBAFIR_MASK_OR");
//set the masks only if the side effect bit is set
if (mbaFir->IsBitSet(2))
{
mbaFirMaskOr->SetBit(2);
l_rc = mbaFirMaskOr->Write();
if (SUCCESS != l_rc)
{
PRDF_ERR(PRDF_FUNC "MBAFIR_MASK_OR write failed for "
"0x%08x", i_mbaChip->GetId());
break;
}
}
if (mbaCalFir->IsBitSet(2))
{
mbaCalMaskOr->SetBit(2);
l_rc = mbaCalMaskOr->Write();
if (SUCCESS != l_rc)
{
PRDF_ERR(PRDF_FUNC "MBACALFIR_MASK_OR write failed for "
"0x%08x", i_mbaChip->GetId());
break;
}
}
if (mbaCalFir->IsBitSet(17))
{
mbaCalMaskOr->SetBit(17);
l_rc = mbaCalMaskOr->Write();
if (SUCCESS != l_rc)
{
PRDF_ERR(PRDF_FUNC "MBACALFIR_MASK_OR write failed for "
"0x%08x", i_mbaChip->GetId());
break;
}
}
if (mbsFir->IsBitSet(4))
{
mbsFirMaskOr->SetBit(4);
l_rc = mbsFirMaskOr->Write();
if (SUCCESS != l_rc)
{
PRDF_ERR(PRDF_FUNC "MBSFIR_MASK_OR write failed for "
"0x%08x", membChip->GetId());
break;
}
}
}while(0);
return SUCCESS;
#undef PRDF_FUNC
}
int32_t CenMbaTdCtlrCommon::checkEccErrors( uint16_t & o_eccErrorMask,
STEP_CODE_DATA_STRUCT & io_sc )
{
#define PRDF_FUNC "[CenMbaTdCtlrCommon::checkEccErrors] "
int32_t o_rc = SUCCESS;
o_eccErrorMask = NO_ERROR;
do
{
const char * reg_str = (0 == iv_mbaPos) ? "MBA0_MBSECCFIR"
: "MBA1_MBSECCFIR";
SCAN_COMM_REGISTER_CLASS * mbsEccFir
= iv_membChip->getRegister( reg_str );
o_rc = mbsEccFir->Read();
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "Read() failed on %s", reg_str );
break;
}
if ( mbsEccFir->IsBitSet(20 + iv_rank.getMaster()) )
{
o_eccErrorMask |= MPE;
io_sc.service_data->AddSignatureList(iv_mbaTrgt, PRDFSIG_MaintMPE);
// Clean up side-effect FIRs that may be set due to the chip mark.
o_rc = chipMarkCleanup();
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "chipMarkCleanup() failed" );
break;
}
}
if ( mbsEccFir->IsBitSet(38) )
{
// No need to add error signature. MCE is not error. It will be
// handled only in VCM/DSD phase 2.
o_eccErrorMask |= MCE;
}
if ( mbsEccFir->IsBitSet(41) )
{
o_eccErrorMask |= UE;
io_sc.service_data->AddSignatureList( iv_mbaTrgt, PRDFSIG_MaintUE );
}
SCAN_COMM_REGISTER_CLASS * mbaSpaFir =
iv_mbaChip->getRegister("MBASPA");
o_rc = mbaSpaFir->Read();
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "Failed to read MBASPA Regsiter");
break;
}
if ( mbaSpaFir->IsBitSet(1) )
{
o_eccErrorMask |= HARD_CTE;
io_sc.service_data->AddSignatureList( iv_mbaTrgt,
PRDFSIG_MaintHARD_CTE );
}
if ( mbaSpaFir->IsBitSet(2) )
{
o_eccErrorMask |= SOFT_CTE;
io_sc.service_data->AddSignatureList( iv_mbaTrgt,
PRDFSIG_MaintSOFT_CTE );
}
if ( mbaSpaFir->IsBitSet(3) )
{
o_eccErrorMask |= INTER_CTE;
io_sc.service_data->AddSignatureList( iv_mbaTrgt,
PRDFSIG_MaintINTER_CTE );
}
if ( mbaSpaFir->IsBitSet(4) )
{
o_eccErrorMask |= RETRY_CTE;
io_sc.service_data->AddSignatureList( iv_mbaTrgt,
PRDFSIG_MaintRETRY_CTE );
}
} while(0);
return o_rc;
#undef PRDF_FUNC
}
/**
* @brief Mask the PLL error for P8 Plugin
* @param i_chip P8 chip
* @param i_sc The step code data struct
* @param i_oscPos active osc position
* @returns Failure or Success of query.
* @note
*/
int32_t MaskPllIo( ExtensibleChip * i_chip,
STEP_CODE_DATA_STRUCT & i_sc,
uint32_t i_oscPos )
{
#define PRDF_FUNC "[Proc::MaskPllIo] "
int32_t rc = SUCCESS;
do
{
if (CHECK_STOP == i_sc.service_data->getPrimaryAttnType())
{
break;
}
if ( i_oscPos >= MAX_PCIE_OSC_PER_NODE )
{
PRDF_ERR(PRDF_FUNC "invalid oscPos: %d for chip: "
"0x%08x", i_oscPos, i_chip->GetId());
rc = FAIL;
break;
}
uint32_t oscPos = getIoOscPos( i_chip, i_sc );
if ( oscPos != i_oscPos )
{
PRDF_DTRAC(PRDF_FUNC "skip masking for chip: 0x%08x, "
"oscPos: %d, i_oscPos: %d",
i_chip->GetId(), oscPos, i_oscPos);
break;
}
// fence off pci osc error reg bit
SCAN_COMM_REGISTER_CLASS * pciConfigReg =
i_chip->getRegister("PCI_CONFIG_REG");
rc = pciConfigReg->Read();
if (rc != SUCCESS)
{
PRDF_ERR(PRDF_FUNC "PCI_CONFIG_REG read failed"
"for 0x%08x", i_chip->GetId());
break;
}
if(!pciConfigReg->IsBitSet(PLL_ERROR_MASK))
{
pciConfigReg->SetBit(PLL_ERROR_MASK);
rc = pciConfigReg->Write();
if (rc != SUCCESS)
{
PRDF_ERR(PRDF_FUNC "PCI_CONFIG_REG write failed"
"for chip: 0x%08x",
i_chip->GetId());
}
}
// Since TP_LFIR bit is the collection of all of the
// pll error reg bits, we can't mask it or we will not
// see any PLL errors reported from the error regs
} while(0);
return rc;
#undef PRDF_FUNC
}
/**
* @brief Clear the PLL error for P8 Plugin
* @param i_chip P8 chip
* @param i_sc The step code data struct
* @returns Failure or Success of query.
*/
int32_t ClearPllIo( ExtensibleChip * i_chip,
STEP_CODE_DATA_STRUCT & i_sc)
{
#define PRDF_FUNC "[Proc::ClearPllIo] "
int32_t rc = SUCCESS;
if (CHECK_STOP != i_sc.service_data->getPrimaryAttnType())
{
// Clear pci osc error reg bit
int32_t tmpRC = SUCCESS;
SCAN_COMM_REGISTER_CLASS * pciErrReg =
i_chip->getRegister("PCI_ERROR_REG");
tmpRC = pciErrReg->Read();
if (tmpRC != SUCCESS)
{
PRDF_ERR(PRDF_FUNC "PCI_ERROR_REG read failed"
"for chip: 0x%08x", i_chip->GetId());
rc |= tmpRC;
}
if( pciErrReg->IsBitSet( PLL_ERROR_BIT ) )
{
pciErrReg->clearAllBits();
pciErrReg->SetBit(PLL_ERROR_BIT);
tmpRC = pciErrReg->Write();
if ( SUCCESS != tmpRC )
{
PRDF_ERR( PRDF_FUNC "Write() failed on PCI Error register: "
"proc=0x%08x", i_chip->GetId() );
rc |= tmpRC;
}
}
// Clear TP_LFIR
SCAN_COMM_REGISTER_CLASS * TP_LFIRand =
i_chip->getRegister("TP_LFIR_AND");
TP_LFIRand->setAllBits();
TP_LFIRand->ClearBit(PLL_DETECT_P8);
tmpRC = TP_LFIRand->Write();
if (tmpRC != SUCCESS)
{
PRDF_ERR(PRDF_FUNC "TP_LFIR_AND write failed"
"for chip: 0x%08x", i_chip->GetId());
rc |= tmpRC;
}
SCAN_COMM_REGISTER_CLASS * oscCerrReg =
i_chip->getRegister("OSCERR");
tmpRC = oscCerrReg->Read();
if (tmpRC != SUCCESS)
{
PRDF_ERR(PRDF_FUNC "OSCERR read failed"
"for 0x%08x", i_chip->GetId());
rc |= tmpRC;
}
oscCerrReg->ClearBit(4);
oscCerrReg->ClearBit(5);
tmpRC = oscCerrReg->Write();
if (tmpRC != SUCCESS)
{
PRDF_ERR(PRDF_FUNC "oscCerrReg write failed"
"for chip: 0x%08x", i_chip->GetId());
rc |= tmpRC;
}
}
if( rc != SUCCESS )
{
PRDF_ERR(PRDF_FUNC "failed for proc: 0x%.8X",
i_chip->GetId());
}
return rc;
#undef PRDF_FUNC
}
/**
* @fn ClearMbaCalSecondaryBits
* @brief Clears MBACAL secondary Fir bits which may come up because of MBSFIR
* @param i_chip The Centaur chip.
* @param i_sc ServiceDataColector.
* @return SUCCESS.
*/
int32_t ClearMbaCalSecondaryBits( ExtensibleChip * i_chip,
STEP_CODE_DATA_STRUCT & i_sc )
{
#define PRDF_FUNC "[ClearMbaCalSecondaryBits ] "
int32_t l_rc = SUCCESS;
do
{
SCAN_COMM_REGISTER_CLASS * mbsFir = i_chip->getRegister("MBSFIR");
SCAN_COMM_REGISTER_CLASS * mbsFirMask =
i_chip->getRegister("MBSFIR_MASK");
l_rc = mbsFir->Read();
l_rc |= mbsFirMask->Read();
if ( SUCCESS != l_rc )
{
PRDF_ERR( PRDF_FUNC"MBSFIR/MBSFIR_MASK read failed"
"for 0x%08x", i_chip->GetId());
break;
}
CenMembufDataBundle * membdb = getMembufDataBundle( i_chip );
for( uint32_t i = 0; i < MAX_MBA_PER_MEMBUF; i++ )
{
ExtensibleChip * mbaChip = membdb->getMbaChip(i);
if ( NULL == mbaChip ) continue;
SCAN_COMM_REGISTER_CLASS * mbaCalFir =
mbaChip->getRegister("MBACALFIR");
if( SUCCESS != mbaCalFir->Read() )
{
// Do not break. Just print error trace and look for
// other MBA.
PRDF_ERR( PRDF_FUNC"MBACALFIR read failed"
"for 0x%08x", mbaChip->GetId());
continue;
}
if( !( mbaCalFir->IsBitSet( 10 ) || mbaCalFir->IsBitSet( 14 ) ))
continue;
SCAN_COMM_REGISTER_CLASS * mbaCalAndFir =
mbaChip->getRegister("MBACALFIR_AND");
mbaCalAndFir->setAllBits();
mbaCalAndFir->ClearBit(10);
mbaCalAndFir->ClearBit(14);
l_rc = mbaCalAndFir->Write();
if ( SUCCESS != l_rc )
{
// Do not break. Just print error trace and look for
// other MBA.
PRDF_ERR( PRDF_FUNC"MBACALFIR_AND write failed"
"for 0x%08x", mbaChip->GetId());
}
}
}while( 0 );
return SUCCESS;
#undef PRDF_FUNC
} PRDF_PLUGIN_DEFINE( Membuf, ClearMbaCalSecondaryBits );
/**
* @fn ClearMbsSecondaryBits
* @brief Clears MBS secondary Fir bits which may come up because of primary
* MBS/MBI FIR bits.
* @param i_chip The Centaur chip.
* @param i_sc ServiceDataColector.
* @return SUCCESS.
*/
int32_t ClearMbsSecondaryBits( ExtensibleChip * i_chip,
STEP_CODE_DATA_STRUCT & i_sc )
{
#define PRDF_FUNC "[ClearMbsSecondaryBits] "
int32_t l_rc = SUCCESS;
do
{
SCAN_COMM_REGISTER_CLASS * mbsFir = i_chip->getRegister("MBSFIR");
SCAN_COMM_REGISTER_CLASS * mbsFirMask =
i_chip->getRegister("MBSFIR_MASK");
SCAN_COMM_REGISTER_CLASS * mbsFirAnd =
i_chip->getRegister("MBSFIR_AND");
l_rc = mbsFir->Read();
l_rc |= mbsFirMask->Read();
if ( SUCCESS != l_rc )
{
PRDF_ERR( PRDF_FUNC"MBSFIR/MBSFIR_MASK read failed"
"for 0x%08x", i_chip->GetId());
break;
}
mbsFirAnd->setAllBits();
if ( mbsFir->IsBitSet(26)
&& mbsFir->IsBitSet(9) && ( ! mbsFirMask->IsBitSet(9)))
{
mbsFirAnd->ClearBit(26);
}
if( mbsFir->IsBitSet(3) || mbsFir->IsBitSet(4) )
{
SCAN_COMM_REGISTER_CLASS * mbiFir = i_chip->getRegister("MBIFIR");
SCAN_COMM_REGISTER_CLASS * mbiFirMask =
i_chip->getRegister("MBIFIR_MASK");
l_rc = mbiFir->Read();
l_rc |= mbiFirMask->Read();
if ( SUCCESS != l_rc )
{
// Do not break from here, just print error trace.
// If there are other secondary bits ( e.g. 26, 27 ),
// we want to clear them.
PRDF_ERR( PRDF_FUNC"MBIFIR/MASK read failed"
"for 0x%08x", i_chip->GetId());
}
else if ( mbiFir->IsBitSet( 0 ) && ( ! mbiFirMask->IsBitSet( 0 )) )
{
mbsFirAnd->ClearBit(3);
mbsFirAnd->ClearBit(4);
}
}
l_rc = mbsFirAnd->Write();
if ( SUCCESS != l_rc )
{
PRDF_ERR( PRDF_FUNC"MBSFIR_AND write failed"
"for 0x%08x", i_chip->GetId());
break;
}
}while( 0 );
return SUCCESS;
#undef PRDF_FUNC
} PRDF_PLUGIN_DEFINE( Membuf, ClearMbsSecondaryBits );
