/**
* @fn MaskMbaCalSecondaryBits
* @brief Mask MBACAL secondary Fir bits which may come up because of L4 UE.
* @param i_chip The Centaur chip.
* @param i_sc ServiceDataColector.
* @return SUCCESS.
*/
int32_t MaskMbaCalSecondaryBits( ExtensibleChip * i_chip,
STEP_CODE_DATA_STRUCT & i_sc )
{
#define PRDF_FUNC "[MaskMbaCalSecondaryBits ] "
int32_t l_rc = SUCCESS;
do
{
CenMembufDataBundle * membdb = getMembufDataBundle( i_chip );
for( uint32_t i = 0; i < MAX_MBA_PER_MEMBUF; i++ )
{
ExtensibleChip * mbaChip = membdb->getMbaChip(i);
if ( NULL == mbaChip ) continue;
SCAN_COMM_REGISTER_CLASS * mbaCalFirMaskOr =
mbaChip->getRegister("MBACALFIR_MASK_OR");
mbaCalFirMaskOr->SetBit(9);
mbaCalFirMaskOr->SetBit(15);
l_rc = mbaCalFirMaskOr->Write();
if ( SUCCESS != l_rc )
{
// Do not break. Just print error trace and look for
// other MBA.
PRDF_ERR( PRDF_FUNC"MBACALFIR_MASK_OR write failed"
"for 0x%08x", mbaChip->GetId());
}
}
}while( 0 );
return SUCCESS;
#undef PRDF_FUNC
} PRDF_PLUGIN_DEFINE( Membuf, MaskMbaCalSecondaryBits );
// Do the setup for mnfg IPL CE
int32_t CenMbaTdCtlr::mnfgCeSetup()
{
#define PRDF_FUNC "[CenMbaTdCtlr::mnfgCeSetup] "
int32_t o_rc = SUCCESS;
do
{
const char * reg_str = (0 == iv_mbaPos) ? "MBA0_MBSTR" : "MBA1_MBSTR";
SCAN_COMM_REGISTER_CLASS * mbstr = iv_membChip->getRegister( reg_str );
// MBSTR's content could be modified from cleanupCmd()
// so we need to refresh
o_rc = mbstr->ForceRead();
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC"Read() failed on %s", reg_str );
break;
}
if ( TPS_PHASE_1 == iv_tdState )
{
// Enable per-symbol error counters to count soft CEs
mbstr->SetBit(55);
mbstr->SetBit(56);
// Disable per-symbol error counters to count hard CEs
mbstr->ClearBit(57);
}
else if ( TPS_PHASE_2 == iv_tdState )
{
// Disable per-symbol error counters to count soft CEs
mbstr->ClearBit(55);
mbstr->ClearBit(56);
// Enable per-symbol error counters to count hard CEs
mbstr->SetBit(57);
}
else
{
PRDF_ERR( PRDF_FUNC"Inavlid State:%u", iv_tdState );
o_rc = FAIL; break;
}
o_rc = mbstr->Write();
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC"Write() failed on %s", reg_str );
break;
}
} while(0);
return o_rc;
#undef PRDF_FUNC
}
/**
* @fn MaskMbsSecondaryBits
* @brief Mask MBS secondary Fir bits which may come up because of L4 UE.
* @param i_chip The Centaur chip.
* @param i_sc ServiceDataColector.
* @return SUCCESS.
*/
int32_t MaskMbsSecondaryBits( ExtensibleChip * i_chip,
STEP_CODE_DATA_STRUCT & i_sc )
{
#define PRDF_FUNC "[MaskMbsSecondaryBits] "
int32_t l_rc = SUCCESS;
do
{
SCAN_COMM_REGISTER_CLASS * mbsFirMaskOr =
i_chip->getRegister("MBSFIR_MASK_OR");
mbsFirMaskOr->SetBit(27);
l_rc = mbsFirMaskOr->Write();
if ( SUCCESS != l_rc )
{
PRDF_ERR( PRDF_FUNC"MBSFIR_MASK_OR write failed"
"for 0x%08x", i_chip->GetId());
break;
}
}while( 0 );
return SUCCESS;
#undef PRDF_FUNC
} PRDF_PLUGIN_DEFINE( Membuf, MaskMbsSecondaryBits );
/**
* @brief Plugin to mask the side effects of an RCD parity error
* @param i_mbaChip A Centaur MBA chip.
* @param i_sc The step code data struct.
* @return SUCCESS
*/
int32_t maskRcdParitySideEffects( ExtensibleChip * i_mbaChip,
STEP_CODE_DATA_STRUCT & i_sc )
{
#define PRDF_FUNC "[maskRcdParitySideEffects] "
int32_t l_rc = SUCCESS;
do
{
//use a data bundle to get the membuf chip
CenMbaDataBundle * mbadb = getMbaDataBundle( i_mbaChip );
ExtensibleChip * membChip = mbadb->getMembChip();
if (NULL == membChip)
{
PRDF_ERR(PRDF_FUNC "getMembChip() failed");
break;
}
//get the masks for each FIR
SCAN_COMM_REGISTER_CLASS * mbsFirMaskOr =
membChip->getRegister("MBSFIR_MASK_OR");
SCAN_COMM_REGISTER_CLASS * mbaCalMaskOr =
i_mbaChip->getRegister("MBACALFIR_MASK_OR");
SCAN_COMM_REGISTER_CLASS * mbaFirMaskOr =
i_mbaChip->getRegister("MBAFIR_MASK_OR");
mbaFirMaskOr->SetBit(2);
mbaCalMaskOr->SetBit(2);
mbaCalMaskOr->SetBit(17);
mbsFirMaskOr->SetBit(4);
l_rc = mbaFirMaskOr->Write();
l_rc |= mbaCalMaskOr->Write();
l_rc |= mbsFirMaskOr->Write();
if (SUCCESS != l_rc)
{
PRDF_ERR(PRDF_FUNC "MBAFIR_MASK_OR/MBACALFIR_MASK_OR/MBSFIR_MASK_OR"
" write failed for 0x%08x", i_mbaChip->GetId());
break;
}
}while(0);
return SUCCESS;
#undef PRDF_FUNC
}
int32_t CenMbaTdCtlrCommon::prepareNextCmd( bool i_clearStats )
{
#define PRDF_FUNC "[CenMbaTdCtlrCommon::prepareNextCmd] "
int32_t o_rc = SUCCESS;
do
{
//----------------------------------------------------------------------
// Clean up previous command
//----------------------------------------------------------------------
o_rc = cleanupPrevCmd();
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "cleanupPrevCmd() failed" );
break;
}
//----------------------------------------------------------------------
// Clear ECC counters
//----------------------------------------------------------------------
const char * reg_str = NULL;
if ( i_clearStats )
{
reg_str = (0 == iv_mbaPos) ? "MBA0_MBSTR" : "MBA1_MBSTR";
SCAN_COMM_REGISTER_CLASS * mbstr =
iv_membChip->getRegister( reg_str );
// MBSTR's content could be modified from cleanupCmd()
// so we need to refresh
o_rc = mbstr->ForceRead();
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "ForceRead() failed on %s", reg_str );
break;
}
mbstr->SetBit(53); // Setting this bit clears all counters.
o_rc = mbstr->Write();
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "Write() failed on %s", reg_str );
break;
}
// Hardware automatically clears bit 53, so flush this register out
// of the register cache to avoid clearing the counters again with
// a write from the out-of-date cached copy.
RegDataCache & cache = RegDataCache::getCachedRegisters();
cache.flush( iv_membChip, mbstr );
}
//----------------------------------------------------------------------
// Clear ECC FIRs
//----------------------------------------------------------------------
reg_str = (0 == iv_mbaPos) ? "MBA0_MBSECCFIR_AND"
: "MBA1_MBSECCFIR_AND";
SCAN_COMM_REGISTER_CLASS * firand = iv_membChip->getRegister( reg_str );
firand->setAllBits();
// Clear all scrub MPE bits.
// This will need to be done when starting a TD procedure or background
// scrubbing. iv_rank may not be set when starting background scrubbing
// and technically there should only be one of these MPE bits on at a
// time so we should not have to worry about losing an attention by
// clearing them all.
firand->SetBitFieldJustified( 20, 8, 0 );
// Clear scrub NCE, SCE, MCE, RCE, SUE, UE bits (36-41)
firand->SetBitFieldJustified( 36, 6, 0 );
o_rc = firand->Write();
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "Write() failed on %s", reg_str );
break;
}
SCAN_COMM_REGISTER_CLASS * spaAnd =
iv_mbaChip->getRegister("MBASPA_AND");
spaAnd->setAllBits();
// Clear threshold exceeded attentions
spaAnd->SetBitFieldJustified( 1, 4, 0 );
o_rc = spaAnd->Write();
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "Write() failed on MBASPA_AND" );
break;
}
} while (0);
return o_rc;
#undef PRDF_FUNC
}
/**
* @brief Mask the PLL error for P8 Plugin
* @param i_chip P8 chip
* @param i_sc The step code data struct
* @param i_oscPos active osc position
* @returns Failure or Success of query.
* @note
*/
int32_t MaskPllIo( ExtensibleChip * i_chip,
STEP_CODE_DATA_STRUCT & i_sc,
uint32_t i_oscPos )
{
#define PRDF_FUNC "[Proc::MaskPllIo] "
int32_t rc = SUCCESS;
do
{
if (CHECK_STOP == i_sc.service_data->getPrimaryAttnType())
{
break;
}
if ( i_oscPos >= MAX_PCIE_OSC_PER_NODE )
{
PRDF_ERR(PRDF_FUNC "invalid oscPos: %d for chip: "
"0x%08x", i_oscPos, i_chip->GetId());
rc = FAIL;
break;
}
uint32_t oscPos = getIoOscPos( i_chip, i_sc );
if ( oscPos != i_oscPos )
{
PRDF_DTRAC(PRDF_FUNC "skip masking for chip: 0x%08x, "
"oscPos: %d, i_oscPos: %d",
i_chip->GetId(), oscPos, i_oscPos);
break;
}
// fence off pci osc error reg bit
SCAN_COMM_REGISTER_CLASS * pciConfigReg =
i_chip->getRegister("PCI_CONFIG_REG");
rc = pciConfigReg->Read();
if (rc != SUCCESS)
{
PRDF_ERR(PRDF_FUNC "PCI_CONFIG_REG read failed"
"for 0x%08x", i_chip->GetId());
break;
}
if(!pciConfigReg->IsBitSet(PLL_ERROR_MASK))
{
pciConfigReg->SetBit(PLL_ERROR_MASK);
rc = pciConfigReg->Write();
if (rc != SUCCESS)
{
PRDF_ERR(PRDF_FUNC "PCI_CONFIG_REG write failed"
"for chip: 0x%08x",
i_chip->GetId());
}
}
// Since TP_LFIR bit is the collection of all of the
// pll error reg bits, we can't mask it or we will not
// see any PLL errors reported from the error regs
} while(0);
return rc;
#undef PRDF_FUNC
}
/**
* @brief Clear the PLL error for P8 Plugin
* @param i_chip P8 chip
* @param i_sc The step code data struct
* @returns Failure or Success of query.
*/
int32_t ClearPllIo( ExtensibleChip * i_chip,
STEP_CODE_DATA_STRUCT & i_sc)
{
#define PRDF_FUNC "[Proc::ClearPllIo] "
int32_t rc = SUCCESS;
if (CHECK_STOP != i_sc.service_data->getPrimaryAttnType())
{
// Clear pci osc error reg bit
int32_t tmpRC = SUCCESS;
SCAN_COMM_REGISTER_CLASS * pciErrReg =
i_chip->getRegister("PCI_ERROR_REG");
tmpRC = pciErrReg->Read();
if (tmpRC != SUCCESS)
{
PRDF_ERR(PRDF_FUNC "PCI_ERROR_REG read failed"
"for chip: 0x%08x", i_chip->GetId());
rc |= tmpRC;
}
if( pciErrReg->IsBitSet( PLL_ERROR_BIT ) )
{
pciErrReg->clearAllBits();
pciErrReg->SetBit(PLL_ERROR_BIT);
tmpRC = pciErrReg->Write();
if ( SUCCESS != tmpRC )
{
PRDF_ERR( PRDF_FUNC "Write() failed on PCI Error register: "
"proc=0x%08x", i_chip->GetId() );
rc |= tmpRC;
}
}
// Clear TP_LFIR
SCAN_COMM_REGISTER_CLASS * TP_LFIRand =
i_chip->getRegister("TP_LFIR_AND");
TP_LFIRand->setAllBits();
TP_LFIRand->ClearBit(PLL_DETECT_P8);
tmpRC = TP_LFIRand->Write();
if (tmpRC != SUCCESS)
{
PRDF_ERR(PRDF_FUNC "TP_LFIR_AND write failed"
"for chip: 0x%08x", i_chip->GetId());
rc |= tmpRC;
}
SCAN_COMM_REGISTER_CLASS * oscCerrReg =
i_chip->getRegister("OSCERR");
tmpRC = oscCerrReg->Read();
if (tmpRC != SUCCESS)
{
PRDF_ERR(PRDF_FUNC "OSCERR read failed"
"for 0x%08x", i_chip->GetId());
rc |= tmpRC;
}
oscCerrReg->ClearBit(4);
oscCerrReg->ClearBit(5);
tmpRC = oscCerrReg->Write();
if (tmpRC != SUCCESS)
{
PRDF_ERR(PRDF_FUNC "oscCerrReg write failed"
"for chip: 0x%08x", i_chip->GetId());
rc |= tmpRC;
}
}
if( rc != SUCCESS )
{
PRDF_ERR(PRDF_FUNC "failed for proc: 0x%.8X",
i_chip->GetId());
}
return rc;
#undef PRDF_FUNC
}
