bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const {
MachineBasicBlock *BB = I.getParent();
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
unsigned Size = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI);
unsigned DstLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
if (Size != 64)
return false;
DebugLoc DL = I.getDebugLoc();
MachineOperand Lo1(getSubOperand64(I.getOperand(1), AMDGPU::sub0));
MachineOperand Lo2(getSubOperand64(I.getOperand(2), AMDGPU::sub0));
BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
.add(Lo1)
.add(Lo2);
MachineOperand Hi1(getSubOperand64(I.getOperand(1), AMDGPU::sub1));
MachineOperand Hi2(getSubOperand64(I.getOperand(2), AMDGPU::sub1));
BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
.add(Hi1)
.add(Hi2);
BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), I.getOperand(0).getReg())
.addReg(DstLo)
.addImm(AMDGPU::sub0)
.addReg(DstHi)
.addImm(AMDGPU::sub1);
for (MachineOperand &MO : I.explicit_operands()) {
if (!MO.isReg() || TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
continue;
RBI.constrainGenericRegister(MO.getReg(), AMDGPU::SReg_64RegClass, MRI);
}
I.eraseFromParent();
return true;
}
// For EVEX instructions that can be encoded using VEX encoding
// replace them by the VEX encoding in order to reduce size.
bool EvexToVexInstPass::CompressEvexToVexImpl(MachineInstr &MI) const {
// VEX format.
// # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1
// [Prefixes] [VEX] OPCODE ModR/M [SIB] [DISP] [IMM]
//
// EVEX format.
// # of bytes: 4 1 1 1 4 / 1 1
// [Prefixes] EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate]
const MCInstrDesc &Desc = MI.getDesc();
// Check for EVEX instructions only.
if ((Desc.TSFlags & X86II::EncodingMask) != X86II::EVEX)
return false;
// Check for EVEX instructions with mask or broadcast as in these cases
// the EVEX prefix is needed in order to carry this information
// thus preventing the transformation to VEX encoding.
if (Desc.TSFlags & (X86II::EVEX_K | X86II::EVEX_B))
return false;
// Check for non EVEX_V512 instrs only.
// EVEX_V512 instr: bit EVEX_L2 = 1; bit VEX_L = 0.
if ((Desc.TSFlags & X86II::EVEX_L2) && !(Desc.TSFlags & X86II::VEX_L))
return false;
// EVEX_V128 instr: bit EVEX_L2 = 0, bit VEX_L = 0.
bool IsEVEX_V128 =
(!(Desc.TSFlags & X86II::EVEX_L2) && !(Desc.TSFlags & X86II::VEX_L));
// EVEX_V256 instr: bit EVEX_L2 = 0, bit VEX_L = 1.
bool IsEVEX_V256 =
(!(Desc.TSFlags & X86II::EVEX_L2) && (Desc.TSFlags & X86II::VEX_L));
unsigned NewOpc = 0;
// Check for EVEX_V256 instructions.
if (IsEVEX_V256) {
// Search for opcode in the EvexToVex256 table.
auto It = EvexToVex256Table.find(MI.getOpcode());
if (It != EvexToVex256Table.end())
NewOpc = It->second;
}
// Check for EVEX_V128 or Scalar instructions.
else if (IsEVEX_V128) {
// Search for opcode in the EvexToVex128 table.
auto It = EvexToVex128Table.find(MI.getOpcode());
if (It != EvexToVex128Table.end())
NewOpc = It->second;
}
if (!NewOpc)
return false;
auto isHiRegIdx = [](unsigned Reg) {
// Check for XMM register with indexes between 16 - 31.
if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
return true;
// Check for YMM register with indexes between 16 - 31.
if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
return true;
return false;
};
// Check that operands are not ZMM regs or
// XMM/YMM regs with hi indexes between 16 - 31.
for (const MachineOperand &MO : MI.explicit_operands()) {
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
assert (!(Reg >= X86::ZMM0 && Reg <= X86::ZMM31));
if (isHiRegIdx(Reg))
return false;
}
const MCInstrDesc &MCID = TII->get(NewOpc);
MI.setDesc(MCID);
MI.setAsmPrinterFlag(AC_EVEX_2_VEX);
return true;
}
