예제 #1
0
CodeGenInstAlias::CodeGenInstAlias(Record *R, unsigned Variant,
                                   CodeGenTarget &T)
    : TheDef(R) {
    Result = R->getValueAsDag("ResultInst");
    AsmString = R->getValueAsString("AsmString");
    AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, Variant);


    // Verify that the root of the result is an instruction.
    DefInit *DI = dyn_cast<DefInit>(Result->getOperator());
    if (!DI || !DI->getDef()->isSubClassOf("Instruction"))
        PrintFatalError(R->getLoc(),
                        "result of inst alias should be an instruction");

    ResultInst = &T.getInstruction(DI->getDef());

    // NameClass - If argument names are repeated, we need to verify they have
    // the same class.
    StringMap<Record*> NameClass;
    for (unsigned i = 0, e = Result->getNumArgs(); i != e; ++i) {
        DefInit *ADI = dyn_cast<DefInit>(Result->getArg(i));
        if (!ADI || Result->getArgName(i).empty())
            continue;
        // Verify we don't have something like: (someinst GR16:$foo, GR32:$foo)
        // $foo can exist multiple times in the result list, but it must have the
        // same type.
        Record *&Entry = NameClass[Result->getArgName(i)];
        if (Entry && Entry != ADI->getDef())
            PrintFatalError(R->getLoc(), "result value $" + Result->getArgName(i) +
                            " is both " + Entry->getName() + " and " +
                            ADI->getDef()->getName() + "!");
        Entry = ADI->getDef();
    }

    // Decode and validate the arguments of the result.
    unsigned AliasOpNo = 0;
    for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {

        // Tied registers don't have an entry in the result dag unless they're part
        // of a complex operand, in which case we include them anyways, as we
        // don't have any other way to specify the whole operand.
        if (ResultInst->Operands[i].MINumOperands == 1 &&
                ResultInst->Operands[i].getTiedRegister() != -1)
            continue;

        if (AliasOpNo >= Result->getNumArgs())
            PrintFatalError(R->getLoc(), "not enough arguments for instruction!");

        Record *InstOpRec = ResultInst->Operands[i].Rec;
        unsigned NumSubOps = ResultInst->Operands[i].MINumOperands;
        ResultOperand ResOp(static_cast<int64_t>(0));
        if (tryAliasOpMatch(Result, AliasOpNo, InstOpRec, (NumSubOps > 1),
                            R->getLoc(), T, ResOp)) {
            // If this is a simple operand, or a complex operand with a custom match
            // class, then we can match is verbatim.
            if (NumSubOps == 1 ||
                    (InstOpRec->getValue("ParserMatchClass") &&
                     InstOpRec->getValueAsDef("ParserMatchClass")
                     ->getValueAsString("Name") != "Imm")) {
                ResultOperands.push_back(ResOp);
                ResultInstOperandIndex.push_back(std::make_pair(i, -1));
                ++AliasOpNo;

                // Otherwise, we need to match each of the suboperands individually.
            } else {
                DagInit *MIOI = ResultInst->Operands[i].MIOperandInfo;
                for (unsigned SubOp = 0; SubOp != NumSubOps; ++SubOp) {
                    Record *SubRec = cast<DefInit>(MIOI->getArg(SubOp))->getDef();

                    // Take care to instantiate each of the suboperands with the correct
                    // nomenclature: $foo.bar
                    ResultOperands.push_back(
                        ResultOperand(Result->getArgName(AliasOpNo) + "." +
                                      MIOI->getArgName(SubOp), SubRec));
                    ResultInstOperandIndex.push_back(std::make_pair(i, SubOp));
                }
                ++AliasOpNo;
            }
            continue;
        }

        // If the argument did not match the instruction operand, and the operand
        // is composed of multiple suboperands, try matching the suboperands.
        if (NumSubOps > 1) {
            DagInit *MIOI = ResultInst->Operands[i].MIOperandInfo;
            for (unsigned SubOp = 0; SubOp != NumSubOps; ++SubOp) {
                if (AliasOpNo >= Result->getNumArgs())
                    PrintFatalError(R->getLoc(), "not enough arguments for instruction!");
                Record *SubRec = cast<DefInit>(MIOI->getArg(SubOp))->getDef();
                if (tryAliasOpMatch(Result, AliasOpNo, SubRec, false,
                                    R->getLoc(), T, ResOp)) {
                    ResultOperands.push_back(ResOp);
                    ResultInstOperandIndex.push_back(std::make_pair(i, SubOp));
                    ++AliasOpNo;
                } else {
                    PrintFatalError(R->getLoc(), "result argument #" + Twine(AliasOpNo) +
                                    " does not match instruction operand class " +
                                    (SubOp == 0 ? InstOpRec->getName() :SubRec->getName()));
                }
            }
            continue;
        }
        PrintFatalError(R->getLoc(), "result argument #" + Twine(AliasOpNo) +
                        " does not match instruction operand class " +
                        InstOpRec->getName());
    }

    if (AliasOpNo != Result->getNumArgs())
        PrintFatalError(R->getLoc(), "too many operands for instruction!");
}
예제 #2
0
CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
  AsmString = R->getValueAsString("AsmString");
  Result = R->getValueAsDag("ResultInst");

  // Verify that the root of the result is an instruction.
  DefInit *DI = dynamic_cast<DefInit*>(Result->getOperator());
  if (DI == 0 || !DI->getDef()->isSubClassOf("Instruction"))
    throw TGError(R->getLoc(), "result of inst alias should be an instruction");

  ResultInst = &T.getInstruction(DI->getDef());

  // NameClass - If argument names are repeated, we need to verify they have
  // the same class.
  StringMap<Record*> NameClass;
  for (unsigned i = 0, e = Result->getNumArgs(); i != e; ++i) {
    DefInit *ADI = dynamic_cast<DefInit*>(Result->getArg(i));
    if (!ADI || Result->getArgName(i).empty())
      continue;
    // Verify we don't have something like: (someinst GR16:$foo, GR32:$foo)
    // $foo can exist multiple times in the result list, but it must have the
    // same type.
    Record *&Entry = NameClass[Result->getArgName(i)];
    if (Entry && Entry != ADI->getDef())
      throw TGError(R->getLoc(), "result value $" + Result->getArgName(i) +
                    " is both " + Entry->getName() + " and " +
                    ADI->getDef()->getName() + "!");
    Entry = ADI->getDef();
  }

  // Decode and validate the arguments of the result.
  unsigned AliasOpNo = 0;
  for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {

    // Tied registers don't have an entry in the result dag.
    if (ResultInst->Operands[i].getTiedRegister() != -1)
      continue;

    if (AliasOpNo >= Result->getNumArgs())
      throw TGError(R->getLoc(), "not enough arguments for instruction!");

    Record *InstOpRec = ResultInst->Operands[i].Rec;
    unsigned NumSubOps = ResultInst->Operands[i].MINumOperands;
    ResultOperand ResOp(static_cast<int64_t>(0));
    if (tryAliasOpMatch(Result, AliasOpNo, InstOpRec, (NumSubOps > 1),
                        R->getLoc(), T, ResOp)) {
      ResultOperands.push_back(ResOp);
      ResultInstOperandIndex.push_back(std::make_pair(i, -1));
      ++AliasOpNo;
      continue;
    }

    // If the argument did not match the instruction operand, and the operand
    // is composed of multiple suboperands, try matching the suboperands.
    if (NumSubOps > 1) {
      DagInit *MIOI = ResultInst->Operands[i].MIOperandInfo;
      for (unsigned SubOp = 0; SubOp != NumSubOps; ++SubOp) {
        if (AliasOpNo >= Result->getNumArgs())
          throw TGError(R->getLoc(), "not enough arguments for instruction!");
        Record *SubRec = dynamic_cast<DefInit*>(MIOI->getArg(SubOp))->getDef();
        if (tryAliasOpMatch(Result, AliasOpNo, SubRec, false,
                            R->getLoc(), T, ResOp)) {
          ResultOperands.push_back(ResOp);
          ResultInstOperandIndex.push_back(std::make_pair(i, SubOp));
          ++AliasOpNo;
        } else {
          throw TGError(R->getLoc(), "result argument #" + utostr(AliasOpNo) +
                        " does not match instruction operand class " +
                        (SubOp == 0 ? InstOpRec->getName() :SubRec->getName()));
        }
      }
      continue;
    }
    throw TGError(R->getLoc(), "result argument #" + utostr(AliasOpNo) +
                  " does not match instruction operand class " +
                  InstOpRec->getName());
  }

  if (AliasOpNo != Result->getNumArgs())
    throw TGError(R->getLoc(), "too many operands for instruction!");
}
예제 #3
0
void CodeEmitterGen::run(raw_ostream &o) {
  CodeGenTarget Target;
  std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
  
  // For little-endian instruction bit encodings, reverse the bit order
  if (Target.isLittleEndianEncoding()) reverseBits(Insts);

  EmitSourceFileHeader("Machine Code Emitter", o);
  std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::";
  
  std::vector<const CodeGenInstruction*> NumberedInstructions;
  Target.getInstructionsByEnumValue(NumberedInstructions);

  // Emit function declaration
  o << "unsigned " << Target.getName() << "CodeEmitter::"
    << "getBinaryCodeForInstr(const MachineInstr &MI) {\n";

  // Emit instruction base values
  o << "  static const unsigned InstBits[] = {\n";
  for (std::vector<const CodeGenInstruction*>::iterator
          IN = NumberedInstructions.begin(),
          EN = NumberedInstructions.end();
       IN != EN; ++IN) {
    const CodeGenInstruction *CGI = *IN;
    Record *R = CGI->TheDef;
    
    if (R->getName() == "PHI" ||
        R->getName() == "INLINEASM" ||
        R->getName() == "DBG_LABEL" ||
        R->getName() == "EH_LABEL" ||
        R->getName() == "GC_LABEL" ||
        R->getName() == "KILL" ||
        R->getName() == "EXTRACT_SUBREG" ||
        R->getName() == "INSERT_SUBREG" ||
        R->getName() == "IMPLICIT_DEF" ||
        R->getName() == "SUBREG_TO_REG" ||
        R->getName() == "COPY_TO_REGCLASS") {
      o << "    0U,\n";
      continue;
    }
    
    BitsInit *BI = R->getValueAsBitsInit("Inst");

    // Start by filling in fixed values...
    unsigned Value = 0;
    for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
      if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
        Value |= B->getValue() << (e-i-1);
      }
    }
    o << "    " << Value << "U," << '\t' << "// " << R->getName() << "\n";
  }
  o << "    0U\n  };\n";
  
  // Map to accumulate all the cases.
  std::map<std::string, std::vector<std::string> > CaseMap;
  
  // Construct all cases statement for each opcode
  for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
        IC != EC; ++IC) {
    Record *R = *IC;
    const std::string &InstName = R->getName();
    std::string Case("");
    
    if (InstName == "PHI" ||
        InstName == "INLINEASM" ||
        InstName == "DBG_LABEL"||
        InstName == "EH_LABEL"||
        InstName == "GC_LABEL"||
        InstName == "KILL"||
        InstName == "EXTRACT_SUBREG" ||
        InstName == "INSERT_SUBREG" ||
        InstName == "IMPLICIT_DEF" ||
        InstName == "SUBREG_TO_REG" ||
        InstName == "COPY_TO_REGCLASS") continue;

    BitsInit *BI = R->getValueAsBitsInit("Inst");
    const std::vector<RecordVal> &Vals = R->getValues();
    CodeGenInstruction &CGI = Target.getInstruction(InstName);
    
    // Loop over all of the fields in the instruction, determining which are the
    // operands to the instruction.
    unsigned op = 0;
    for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
      if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) {
        // Is the operand continuous? If so, we can just mask and OR it in
        // instead of doing it bit-by-bit, saving a lot in runtime cost.
        const std::string &VarName = Vals[i].getName();
        bool gotOp = false;
        
        for (int bit = BI->getNumBits()-1; bit >= 0; ) {
          int varBit = getVariableBit(VarName, BI, bit);
          
          if (varBit == -1) {
            --bit;
          } else {
            int beginInstBit = bit;
            int beginVarBit = varBit;
            int N = 1;
            
            for (--bit; bit >= 0;) {
              varBit = getVariableBit(VarName, BI, bit);
              if (varBit == -1 || varBit != (beginVarBit - N)) break;
              ++N;
              --bit;
            }

            if (!gotOp) {
              /// If this operand is not supposed to be emitted by the generated
              /// emitter, skip it.
              while (CGI.isFlatOperandNotEmitted(op))
                ++op;
              
              Case += "      // op: " + VarName + "\n"
                   +  "      op = getMachineOpValue(MI, MI.getOperand("
                   +  utostr(op++) + "));\n";
              gotOp = true;
            }
            
            unsigned opMask = ~0U >> (32-N);
            int opShift = beginVarBit - N + 1;
            opMask <<= opShift;
            opShift = beginInstBit - beginVarBit;
            
            if (opShift > 0) {
              Case += "      Value |= (op & " + utostr(opMask) + "U) << "
                   +  itostr(opShift) + ";\n";
            } else if (opShift < 0) {
              Case += "      Value |= (op & " + utostr(opMask) + "U) >> "
                   +  itostr(-opShift) + ";\n";
            } else {
              Case += "      Value |= op & " + utostr(opMask) + "U;\n";
            }
          }
        }
      }
    }

    std::vector<std::string> &InstList = CaseMap[Case];
    InstList.push_back(InstName);
  }


  // Emit initial function code
  o << "  const unsigned opcode = MI.getOpcode();\n"
    << "  unsigned Value = InstBits[opcode];\n"
    << "  unsigned op = 0;\n"
    << "  op = op;  // suppress warning\n"
    << "  switch (opcode) {\n";

  // Emit each case statement
  std::map<std::string, std::vector<std::string> >::iterator IE, EE;
  for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
    const std::string &Case = IE->first;
    std::vector<std::string> &InstList = IE->second;

    for (int i = 0, N = InstList.size(); i < N; i++) {
      if (i) o << "\n";
      o << "    case " << Namespace << InstList[i]  << ":";
    }
    o << " {\n";
    o << Case;
    o << "      break;\n"
      << "    }\n";
  }

  // Default case: unhandled opcode
  o << "  default:\n"
    << "    std::string msg;\n"
    << "    raw_string_ostream Msg(msg);\n"
    << "    Msg << \"Not supported instr: \" << MI;\n"
    << "    llvm_report_error(Msg.str());\n"
    << "  }\n"
    << "  return Value;\n"
    << "}\n\n";
}
예제 #4
0
CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
  AsmString = R->getValueAsString("AsmString");
  Result = R->getValueAsDag("ResultInst");

  // Verify that the root of the result is an instruction.
  DefInit *DI = dynamic_cast<DefInit*>(Result->getOperator());
  if (DI == 0 || !DI->getDef()->isSubClassOf("Instruction"))
    throw TGError(R->getLoc(), "result of inst alias should be an instruction");

  ResultInst = &T.getInstruction(DI->getDef());
  
  // NameClass - If argument names are repeated, we need to verify they have
  // the same class.
  StringMap<Record*> NameClass;
    
  // Decode and validate the arguments of the result.
  unsigned AliasOpNo = 0;
  for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
    // Tied registers don't have an entry in the result dag.
    if (ResultInst->Operands[i].getTiedRegister() != -1)
      continue;

    if (AliasOpNo >= Result->getNumArgs())
      throw TGError(R->getLoc(), "result has " + utostr(Result->getNumArgs()) +
                    " arguments, but " + ResultInst->TheDef->getName() +
                    " instruction expects " +
                    utostr(ResultInst->Operands.size()) + " operands!");
    
    
    Init *Arg = Result->getArg(AliasOpNo);
    Record *ResultOpRec = ResultInst->Operands[i].Rec;

    // Handle explicit registers.
    if (DefInit *ADI = dynamic_cast<DefInit*>(Arg)) {
      if (ADI->getDef()->isSubClassOf("Register")) {
        if (!Result->getArgName(AliasOpNo).empty())
          throw TGError(R->getLoc(), "result fixed register argument must "
                        "not have a name!");
        
        if (!ResultOpRec->isSubClassOf("RegisterClass"))
          throw TGError(R->getLoc(), "result fixed register argument is not "
                        "passed to a RegisterClass operand!");
        
        if (!T.getRegisterClass(ResultOpRec).containsRegister(ADI->getDef()))
          throw TGError(R->getLoc(), "fixed register " +ADI->getDef()->getName()
                        + " is not a member of the " + ResultOpRec->getName() +
                        " register class!");
                                                                              
        // Now that it is validated, add it.
        ResultOperands.push_back(ResultOperand(ADI->getDef()));
        ++AliasOpNo;
        continue;
      }
    }
    
    // If the operand is a record, it must have a name, and the record type must
    // match up with the instruction's argument type.
    if (DefInit *ADI = dynamic_cast<DefInit*>(Arg)) {
      if (Result->getArgName(AliasOpNo).empty())
        throw TGError(R->getLoc(), "result argument #" + utostr(AliasOpNo) +
                      " must have a name!");

      if (ADI->getDef() != ResultOpRec)
        throw TGError(R->getLoc(), "result argument #" + utostr(AliasOpNo) +
                      " declared with class " + ADI->getDef()->getName() +
                      ", instruction operand is class " + 
                      ResultOpRec->getName());
      
      // Verify we don't have something like: (someinst GR16:$foo, GR32:$foo)
      // $foo can exist multiple times in the result list, but it must have the
      // same type.
      Record *&Entry = NameClass[Result->getArgName(AliasOpNo)];
      if (Entry && Entry != ADI->getDef())
        throw TGError(R->getLoc(), "result value $" +
                      Result->getArgName(AliasOpNo) +
                      " is both " + Entry->getName() + " and " +
                      ADI->getDef()->getName() + "!");
      
      // Now that it is validated, add it.
      ResultOperands.push_back(ResultOperand(Result->getArgName(AliasOpNo),
                                             ADI->getDef()));
      ++AliasOpNo;
      continue;
    }
    
    if (IntInit *II = dynamic_cast<IntInit*>(Arg)) {
      // Integer arguments can't have names.
      if (!Result->getArgName(AliasOpNo).empty())
        throw TGError(R->getLoc(), "result argument #" + utostr(AliasOpNo) +
                      " must not have a name!");
      if (ResultInst->Operands[i].MINumOperands != 1 ||
          !ResultOpRec->isSubClassOf("Operand"))
        throw TGError(R->getLoc(), "invalid argument class " + 
                      ResultOpRec->getName() +
                      " for integer result operand!");
      ResultOperands.push_back(ResultOperand(II->getValue()));
      ++AliasOpNo;
      continue;
    }

    throw TGError(R->getLoc(), "result of inst alias has unknown operand type");
  }
  
  if (AliasOpNo != Result->getNumArgs())
    throw TGError(R->getLoc(), "result has " + utostr(Result->getNumArgs()) +
                  " arguments, but " + ResultInst->TheDef->getName() +
                  " instruction expects " + utostr(ResultInst->Operands.size())+
                  " operands!");
}