void Circuit::logicSim( Pattern* PatternSet )
{
AssignPiValue( PatternSet );
for(unsigned i = 0 ; i < topologicalSequence.size() ; ++i)
{
int gateID = topologicalSequence[i];
Gate targetGate = gate(gateID);
// PI = 1, PO = 2, CUT = 3, CUT_BAR = 4, TIE0 = 5, TIE1 = 6, NORMAL = 7, REMOVED = 8, UNUSED = 0
int finalValue = value[targetGate.inWire(0)];
for(unsigned j = 1 ; j < targetGate.numInWire() ; ++j)
{
int inWireID = targetGate.inWire(j);
//assert(level[wire(inWireID).preGate()] <= level[gateID]);
int inValue = value[inWireID];
switch(targetGate.typeID())
{
case 1:
case 2:
finalValue = inValue;
break;
case 3:
case 4:
finalValue = finalValue & inValue;
break;
case 5:
case 6:
finalValue = finalValue | inValue;
break;
case 7:
case 8:
finalValue = finalValue ^ inValue;
break;
default:
cout << "strange gate type id: " << targetGate.typeID() << endl;
exit(0);
}
}
switch(targetGate.typeID())
{
case 1:
case 4:
case 6:
case 8:
finalValue = ~ finalValue;
break;
default:
break;
}
///cout<< finalValue<<endl;
Wire fanoutWire = wire( targetGate.outWire() );
if( fanoutWire.type() != "CUT" && fanoutWire.type() != "CUT_BAR" )
{
wire( targetGate.outWire() ).setValueSet( finalValue );
value[ targetGate.outWire() ] = finalValue;
}
}
return;
}
