int main()
{
Vec<ZZ> v;
ZZ a,b,c;
a = 2;
b=3;
c=4;
v.append(a);
v.append(b);
v.append(c);
for(int i=0; i<v.length(); i++)
{
cout << v[i] / 2 << endl;
}
/*
ZZ a, b, c;
cin >> a;
cin >> b;
c = (a+1)*(b+1);
cout << c << "\n";
ZZ acc, val;
acc = 0;
while (cin >> val)
acc += val*val;
cout << acc << "\n";*/
return 0;
}
static bool assign_port_rec( Vec<InstAndPort> &assigned_ports, Inst *inst, int ninp, CppOutReg *out_reg ) {
Vec<InstAndPort> assigned_ports_trial;
// ok ?
if ( _assign_port_rec( assigned_ports_trial, inst, ninp, out_reg ) ) {
assigned_ports.append( assigned_ports_trial );
return true;
}
// else, undo out_reg assignations
for( InstAndPort &a : assigned_ports_trial )
clear_port( a );
return false;
}
bool push(T t) { return back->append(t); }
