void ArchFile::parse(Design* design, NLFactory* factory){
std::ifstream infile(getfilename().c_str());
assert(infile);
string line;
XML_TAG tag;
Port* curPort;
Cell* curCell;
Net* curNet;
Instance* curInstance;
Library* curLibrary;
using std::cerr;
#ifdef Debug
int line_lndex=0;
int count_of_XMLTAGIGNORE=0;
#endif
while (getline(infile,line)){
tag = getxmltag(line);
if (StartElement(line)){
if (tag == DESIGN){
design->rename(getvalue(line,"name",'\"').c_str());
FPGADesign* fpga = static_cast<FPGADesign*>(design);
fpga->setscale(getposition(getvalue(line,"scale",'\"')));
}
else if (tag == LIBRARY){
string name = getvalue(line,"name",'\"');
curLibrary = factory->makeLibrary(name.c_str(),const_cast<const Design*>(design));
stage = hierarchy_map(name);
}
else if (tag == CELL){
if (stage == TILE){
ArchFactory* af = static_cast<ArchFactory*>(factory);
curCell = af->makeTile(getvalue(line,"name",'\"').c_str(),getvalue(line,"type",'\"').c_str(),curLibrary);
}
else{
curCell = factory->makeCell(getvalue(line,"name",'\"').c_str(),getvalue(line,"type",'\"').c_str(),curLibrary);
static_cast<ArchCell*>(curCell)->sethierarchy(stage);
}
}
else if (tag == PORT){
ArchPort* archport;
ArchPin* cellpin;
string port_name = getvalue(line,"name",'\"');
string prefix = getletters(port_name);
if (stage == TILE){
short msb = str2num(getvalue(line,"msb",'\"'));
short lsb = str2num(getvalue(line,"lsb",'\"'));
SIDE side = str_side_map(getvalue(line,"side",'\"'));
for (short i = lsb; i <= msb; ++i){
string single = prefix + num2str(i);
curPort = factory->makePort(single.c_str(),curCell);
archport = static_cast<ArchPort*>(curPort);
cellpin = factory->makePin(single.c_str(),NULL);
archport->setserial(i);
archport->setside(side);
archport->setcellpin(cellpin);
cellpin->setcellport(curPort);
curCell->addport(curPort);
}
}
else{
curPort = factory->makePort(port_name.c_str(),curCell);
archport = static_cast<ArchPort*>(curPort);
cellpin = factory->makePin(port_name.c_str(),NULL);
archport->setdir(dir_map(getvalue(line,"direction",'\"')));
archport->setcellpin(cellpin);
cellpin->setcellport(curPort);
curCell->addport(curPort);
}
}
else if (tag == PATH)
{
//more information to add: segregated, cin, cout, r, delay and so on
ArchCell::const_port_iter from,to;
if( !curCell->findport(from,getvalue(line,"from",'\"')) ){cerr<<"something wrong here."<<"file: "<<__FILE__<<" line"<<__LINE__<<endl;} //modification 1
if( !curCell->findport(to,getvalue(line,"to",'\"'))){cerr<<"something wrong here."<<"file: "<<__FILE__<<" line"<<__LINE__<<endl;}
(static_cast<ArchCell*>(curCell))->creatpath(const_cast<Pin*>((*from)->getcellpin()),const_cast<Pin*>((*to)->getcellpin()));
}
else if (tag == INSTANCE)
{
string tmp_inst_name = getvalue(line,"name",'\"');
string cellRef = getvalue(line,"cellRef",'\"');
string libraryRef = getvalue(line,"libraryRef",'\"');
Design::const_lib_iter lib;
Library::const_cell_iter cell;
bool b1 = design->findlib(lib,libraryRef);
assert(b1);
bool b2 = (*lib)->findelem(cell,cellRef);
assert(b2);
ArchCell* instof = static_cast<ArchCell*>(*cell);
if(stage == ARCH)
curInstance = factory->makeInstance(tmp_inst_name.c_str(),NULL,instof);
else
curInstance = factory->makeInstance(tmp_inst_name.c_str(),curCell,instof);
if (stage == TILE)
(static_cast<ArchInstance*>(curInstance))->setposition(getposition(getvalue(line,"z",'\"')));// the third index of pos for slice or GRM.
else if (stage==ARCH)
(static_cast<ArchInstance*>(curInstance))->setposition(getposition(getvalue(line,"pos",'\"')));
}
else if (tag == NET)
{
curNet = factory->makeNet(getvalue(line,"name",'\"').c_str(),curCell);
}
else if (tag == PORTREF)
{
string::size_type pos = line.find("instanceRef");
string pname = getvalue(line,"name",'\"');
if (pos != string::npos)
{
string instRef = getvalue(line,"instanceRef",'\"');
Cell::const_inst_iter instIter;
Instance::const_pin_iter pinIter;
bool b1 = curCell->findinst(instIter,instRef);
assert(b1);
bool b2 = (*instIter)->findpin(pinIter,pname);
assert(b2);
if(!(b1&&b2)){cerr<<"something wrong here"<<"file: "<<__FILE__<<" line"<<__LINE__<<endl;} //modification3
curNet->addpin(*pinIter);
(*pinIter)->addnet(curNet);
}
else
{
Cell::const_port_iter portIter;
bool temp=curCell->findport(portIter,pname);assert(temp);
Pin* cellpin = const_cast<Pin*>((*portIter)->getcellpin());
curNet->addpin(cellpin);
cellpin->addnet(curNet);
}
}
}
#ifdef Debug
++line_lndex;
if(tag==XMLTAGIGNORE&&line.find("interface")==string::npos&&line.find("content")==string::npos)
{
count_of_XMLTAGIGNORE++;
if(count_of_XMLTAGIGNORE>10)
{
cout<<"too many XMLTAGIGNORE lines exits! make sure it is OK and continue"<<endl;
system("pause");
count_of_XMLTAGIGNORE=0;
}
}
#endif
if (EndElement(line))
{
if (tag == DESIGN){
cout<<"Read arch complete!"<<endl;
}
else if (tag == LIBRARY){
stage = HIEIGNORE;
design->addlib(curLibrary);
}
else if (tag == CELL){
curLibrary->addelem(curCell);
}
else if (tag == PATH){
assert(stage == ELEMENT);
}
else if (tag == INSTANCE){
if (stage == ARCH)
design->addinst(curInstance);
else
curCell->addinst(curInstance);
}
else if (tag == NET){
curCell->addnet(curNet);
}
}
}
infile.close();
}
