/**
* Function IsSame
* test is 2 zones are equivalent:
* 2 zones are equivalent if they have same parameters and same outlines
* info relative to filling is not take in account
* @param aZoneToCompare = zone to compare with "this"
*/
bool ZONE_CONTAINER::IsSame( const ZONE_CONTAINER& aZoneToCompare )
{
// compare basic parameters:
if( GetLayer() != aZoneToCompare.GetLayer() )
return false;
if( GetNetCode() != aZoneToCompare.GetNetCode() )
return false;
if( GetPriority() != aZoneToCompare.GetPriority() )
return false;
// Compare zone specific parameters
if( GetIsKeepout() != aZoneToCompare.GetIsKeepout() )
return false;
if( GetIsKeepout() )
{
if( GetDoNotAllowCopperPour() != aZoneToCompare.GetDoNotAllowCopperPour() )
return false;
if( GetDoNotAllowVias() != aZoneToCompare.GetDoNotAllowVias() )
return false;
if( GetDoNotAllowTracks() != aZoneToCompare.GetDoNotAllowTracks() )
return false;
}
if( m_ArcToSegmentsCount != aZoneToCompare.GetArcSegmentCount() )
return false;
if( m_ZoneClearance != aZoneToCompare.m_ZoneClearance )
return false;
if( m_ZoneMinThickness != aZoneToCompare.GetMinThickness() )
return false;
if( m_FillMode != aZoneToCompare.GetFillMode() )
return false;
if( m_PadConnection != aZoneToCompare.m_PadConnection )
return false;
if( m_ThermalReliefGap != aZoneToCompare.m_ThermalReliefGap )
return false;
if( m_ThermalReliefCopperBridge != aZoneToCompare.m_ThermalReliefCopperBridge )
return false;
// Compare outlines
wxASSERT( m_Poly ); // m_Poly == NULL Should never happen
wxASSERT( aZoneToCompare.Outline() );
if( Outline()->m_CornersList.GetList() !=
aZoneToCompare.Outline()->m_CornersList.GetList() ) // Compare vector
return false;
return true;
}
void DRC::testKeepoutAreas()
{
// Test keepout areas for vias, tracks and pads inside keepout areas
for( int ii = 0; ii < m_pcb->GetAreaCount(); ii++ )
{
ZONE_CONTAINER* area = m_pcb->GetArea( ii );
if( !area->GetIsKeepout() )
continue;
for( TRACK* segm = m_pcb->m_Track; segm != NULL; segm = segm->Next() )
{
if( segm->Type() == PCB_TRACE_T )
{
if( ! area->GetDoNotAllowTracks() )
continue;
if( segm->GetLayer() != area->GetLayer() )
continue;
if( area->Outline()->Distance( segm->GetStart(), segm->GetEnd(),
segm->GetWidth() ) == 0 )
{
m_currentMarker = fillMarker( segm, NULL,
DRCE_TRACK_INSIDE_KEEPOUT, m_currentMarker );
m_pcb->Add( m_currentMarker );
m_mainWindow->GetGalCanvas()->GetView()->Add( m_currentMarker );
m_currentMarker = 0;
}
}
else if( segm->Type() == PCB_VIA_T )
{
if( ! area->GetDoNotAllowVias() )
continue;
if( ! ((VIA*)segm)->IsOnLayer( area->GetLayer() ) )
continue;
if( area->Outline()->Distance( segm->GetPosition() ) < segm->GetWidth()/2 )
{
m_currentMarker = fillMarker( segm, NULL,
DRCE_VIA_INSIDE_KEEPOUT, m_currentMarker );
m_pcb->Add( m_currentMarker );
m_mainWindow->GetGalCanvas()->GetView()->Add( m_currentMarker );
m_currentMarker = 0;
}
}
}
// Test pads: TODO
}
}
bool DRC::doTrackKeepoutDrc( TRACK* aRefSeg )
{
// Test keepout areas for vias, tracks and pads inside keepout areas
for( int ii = 0; ii < m_pcb->GetAreaCount(); ii++ )
{
ZONE_CONTAINER* area = m_pcb->GetArea( ii );
if( !area->GetIsKeepout() )
continue;
if( aRefSeg->Type() == PCB_TRACE_T )
{
if( ! area->GetDoNotAllowTracks() )
continue;
if( aRefSeg->GetLayer() != area->GetLayer() )
continue;
if( area->Outline()->Distance( aRefSeg->GetStart(), aRefSeg->GetEnd(),
aRefSeg->GetWidth() ) == 0 )
{
m_currentMarker = fillMarker( aRefSeg, NULL,
DRCE_TRACK_INSIDE_KEEPOUT, m_currentMarker );
return false;
}
}
else if( aRefSeg->Type() == PCB_VIA_T )
{
if( ! area->GetDoNotAllowVias() )
continue;
if( ! ((VIA*)aRefSeg)->IsOnLayer( area->GetLayer() ) )
continue;
if( area->Outline()->Distance( aRefSeg->GetPosition() ) < aRefSeg->GetWidth()/2 )
{
m_currentMarker = fillMarker( aRefSeg, NULL,
DRCE_VIA_INSIDE_KEEPOUT, m_currentMarker );
return false;
}
}
}
return true;
}
